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authorShelley Chen <shchen@google.com>2023-11-07 13:31:31 -0800
committerShelley Chen <shchen@google.com>2023-11-09 16:36:38 +0000
commitb14b08790fcfd54ba5a9e1e732104c6b756d7ff8 (patch)
tree3362f5166a9537b29dbc5e83302c3c10a0f36032
parenta2bc2540c2d004b475b401ccf0b162c2452857bb (diff)
mb/google/brox: Remove use of EC_IN_RW_OD GPIO
Later GSCs don't need a EC_IN_RW GPIO anymore, so removing the use of this for get_ec_is_trusted(). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I29f94969e9f2c1f239d9f9655f39b8410296f695 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
-rw-r--r--src/mainboard/google/brox/chromeos.c8
-rw-r--r--src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h2
2 files changed, 1 insertions, 9 deletions
diff --git a/src/mainboard/google/brox/chromeos.c b/src/mainboard/google/brox/chromeos.c
index 5c99371eb1..d0fc9f9e77 100644
--- a/src/mainboard/google/brox/chromeos.c
+++ b/src/mainboard/google/brox/chromeos.c
@@ -12,7 +12,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
@@ -21,9 +21,3 @@ int get_write_protect_state(void)
{
return gpio_get(GPIO_PCH_WP);
}
-
-int get_ec_is_trusted(void)
-{
- /* EC is trusted if not in RW. */
- return !gpio_get(GPIO_EC_IN_RW);
-}
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
index 0de7ffd36c..794394fc72 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
+++ b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
@@ -12,8 +12,6 @@
#define GPE_EC_WAKE GPE0_DW2_17
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E15
-/* EC in RW or RO */
-#define GPIO_EC_IN_RW GPP_F18
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_F9
/* GPIO IRQ for tight timestamps / wake support */