diff options
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-06-15 17:26:31 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-17 17:05:58 +0000 |
| commit | b10afbd2e2a8326fb21dc726a6c2bd53b06eb010 (patch) | |
| tree | 84ccad4d25ce713d2733eb8b0e6a6815f65627b6 | |
| parent | e4aa07e2bda92b7beacc5b1cd7ca88cefde0f531 (diff) | |
mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/gpio_m.c | 4 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ae248429a9..4d32ce9135 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -86,6 +86,10 @@ chip soc/intel/alderlake [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" + # Disable DDI ports HPD + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + # TCSS USB3 register "TcssAuxOri" = "0" diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 6f89fd2240..d5eeffa1c4 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -110,7 +110,9 @@ static const struct pad_config gpio_table[] = { /* HPD_1 (E14) and HPD_2 (A18) pins */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), /* GPIO pin for PCIE SRCCLKREQB */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), |