diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-07 09:18:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-22 12:49:12 +0000 |
| commit | aec294a71ac3bf9438a7c43efd519630bd52130b (patch) | |
| tree | ba7f7c341dd37894c5e89618663e7b58296b7f99 | |
| parent | adaab4a97edd37feb1049119a0447cc6fc843e61 (diff) | |
include/spd.h: Fix comment module type information
Change-Id: I7af61404d11f7e0ff5f30c42958c4dd9318538fa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/include/spd.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/include/spd.h b/src/include/spd.h index ca78d9ce98..7a6e5ab7e0 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,7 +201,7 @@ enum spd_memory_type { #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 3: Module type information */ +/* Byte 20 [5:0]: DDR2 Module type information */ enum ddr2_module_type { DDR2_SPD_RDIMM = 0x01, DDR2_SPD_UDIMM = 0x02, @@ -213,6 +213,7 @@ enum ddr2_module_type { DDR2_SPD_MINI_UDIMM = 0x20, }; +/* Byte 3 [3:0]: DDR3 Module type information */ enum ddr3_module_type { DDR3_SPD_RDIMM = 0x01, DDR3_SPD_UDIMM = 0x02, @@ -229,6 +230,7 @@ enum ddr3_module_type { DDR3_SPD_32B_SO_RDIMM = 0x0d, }; +/* Byte 3 [3:0]: DDR4 Module type information */ enum ddr4_module_type { DDR4_SPD_RDIMM = 0x01, DDR4_SPD_UDIMM = 0x02, |