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authorAngel Pons <th3fanbus@gmail.com>2021-06-14 10:57:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-06-16 09:55:40 +0000
commitae7e793a2071430e882bf94b3ff57a16fd7e154b (patch)
treebb55e41144e143ec38570ad1c2a21149464969e2
parent02e534d8b2ebe099866ea396feaf0e09dbeefe58 (diff)
soc/intel/broadwell: Include `pci_irqs.asl` from PCH
Move the inclusion of `pci_irqs.asl` into PCH scope in order to allow deduplicating northbridge ACPI code. Change-Id: I541913226b26662f3798ae9c25ab1ac33cf2ed45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/soc/intel/broadwell/acpi/hostbridge.asl3
-rw-r--r--src/soc/intel/broadwell/pch/acpi/pch.asl3
-rw-r--r--src/soc/intel/broadwell/pch/acpi/pci_irqs.asl (renamed from src/soc/intel/broadwell/acpi/pci_irqs.asl)0
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl
index cf8a6ce5c7..6235f397ff 100644
--- a/src/soc/intel/broadwell/acpi/hostbridge.asl
+++ b/src/soc/intel/broadwell/acpi/hostbridge.asl
@@ -193,9 +193,6 @@ Device (PDRC)
}
}
-/* PCI IRQ assignment */
-#include "pci_irqs.asl"
-
/* Configurable TDP */
#include <northbridge/intel/haswell/acpi/ctdp.asl>
diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl
index 0e90c957d4..fd23f8957b 100644
--- a/src/soc/intel/broadwell/pch/acpi/pch.asl
+++ b/src/soc/intel/broadwell/pch/acpi/pch.asl
@@ -2,6 +2,9 @@
#include <soc/iomap.h>
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
Scope (\)
{
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/pch/acpi/pci_irqs.asl
index e1cfd16c92..e1cfd16c92 100644
--- a/src/soc/intel/broadwell/acpi/pci_irqs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/pci_irqs.asl