coreboot: rk3288: Add a stub implementation of the rk3288 SOC

Most things still needs to be filled in, but this will allow us to build boards which use this SOC.

BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot

Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205069
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239
Reviewed-on: http://review.coreboot.org/8653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

21 files changed, 983 insertions, 0 deletions

diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
index 210bf46c05..fb1ead6c16 100644
--- a/src/mainboard/google/Kconfig
+++ b/src/mainboard/google/Kconfig
@@ -59,6 +59,8 @@ config BOARD_GOOGLE_STORM
 	bool "Storm"
 config BOARD_GOOGLE_STOUT
 	bool "Stout"
+config BOARD_GOOGLE_VEYRON
+	bool "Veyron"
 
 endchoice
 
@@ -81,6 +83,7 @@ source "src/mainboard/google/samus/Kconfig"
 source "src/mainboard/google/slippy/Kconfig"
 source "src/mainboard/google/storm/Kconfig"
 source "src/mainboard/google/stout/Kconfig"
+source "src/mainboard/google/veyron/Kconfig"
 
 config MAINBOARD_VENDOR
 	string "Mainboard Vendor"
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
new file mode 100644
index 0000000000..bbbc617d92
--- /dev/null
+++ b/src/mainboard/google/veyron/Kconfig
@@ -0,0 +1,59 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_GOOGLE_VEYRON
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CHROMEOS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select SOC_ROCKCHIP_RK3288
+	select MAINBOARD_DO_NATIVE_VGA_INIT
+	select BOARD_ROMSIZE_KB_4096
+
+config MAINBOARD_DIR
+	string
+	default google/veyron
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Veyron"
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	hex
+	default 1
+
+config DRAM_DMA_START
+	hex
+	default 0x10000000
+
+config DRAM_DMA_SIZE
+	hex
+	default 0x00200000
+
+config DRAM_SIZE_MB
+	int
+	default 2048
+
+endif #  BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc
new file mode 100644
index 0000000000..50a6ba039b
--- /dev/null
+++ b/src/mainboard/google/veyron/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-y += romstage.c
+ramstage-y += mainboard.c
+ramstage-y += chromeos.c
+
diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c
new file mode 100644
index 0000000000..f396b4b016
--- /dev/null
+++ b/src/mainboard/google/veyron/chromeos.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+
+}
+
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+int get_write_protect_state(void)
+{
+	return 0;
+}
diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb
new file mode 100644
index 0000000000..0acbae9e18
--- /dev/null
+++ b/src/mainboard/google/veyron/devicetree.cb
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# TODO fill with Versatile Express board data in QEMU.
+chip soc/rockchip/rk3288
+	device cpu_cluster 0 on end
+	#SCREEN_RGB
+	register "screen_type" = "2"
+	#LVDS_8BIT_2
+	register "lvds_format" = "1"
+	#OUT_D888_P666
+	register "out_face"    = "33"
+	register "clock_frequency" = "71000000"
+	register "hactive" = "1280"
+	register "vactive" = "800"
+	register "hback_porch" = "100"
+	register "hfront_porch" = "18"
+	register "vback_porch" = "8"
+	register "vfront_porch" = "6"
+	register "hsync_len" = "10"
+	register "vsync_len" = "2"
+	register "hsync_active" = "0"
+	register "vsync_active" = "0"
+	register "de_active" = "0"
+	register "pixelclk_active" = "0"
+	register "swap_rb" = "0"
+	register "swap_rg" = "0"
+	register "swap_gb" = "0"
+	#LCD_EN_GPIO:GPIO7_A3
+	register "lcd_en_gpio" = "0xff7e0004"
+	#LCD_CS_GPIO:GPIO7_A4
+	register "lcd_cs_gpio" = "0xff7e0005"
+end
diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c
new file mode 100644
index 0000000000..607b1d5bbe
--- /dev/null
+++ b/src/mainboard/google/veyron/mainboard.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/cache.h>
+#include <delay.h>
+#include <edid.h>
+#include <vbe.h>
+#include <boot/coreboot_tables.h>
+
+static void mainboard_init(device_t dev)
+{
+
+}
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
+
+void lb_board(struct lb_header *header)
+{
+	struct lb_range *dma;
+
+	dma = (struct lb_range *)lb_new_record(header);
+	dma->tag = LB_TAB_DMA;
+	dma->size = sizeof(*dma);
+	dma->range_start = CONFIG_DRAM_DMA_START;
+	dma->range_size = CONFIG_DRAM_DMA_SIZE;
+}
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
new file mode 100644
index 0000000000..b9daefe6b9
--- /dev/null
+++ b/src/mainboard/google/veyron/romstage.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <armv7.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <delay.h>
+#include <timestamp.h>
+#include <arch/cache.h>
+#include <arch/exception.h>
+
+void main(void)
+{
+	void *entry;
+
+	console_init();
+
+	/* used for MMU and CBMEM setup, in MB */
+	u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
+	u32 dram_size = CONFIG_DRAM_SIZE_MB;
+	u32 dram_end = dram_start + dram_size;
+	mmu_init();
+	/* Device memory below DRAM is uncached. */
+	mmu_config_range(0, dram_start, DCACHE_OFF);
+	/* DRAM is cached. */
+	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+	/* A window for DMA is uncached. */
+	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
+			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+	/* The space above DRAM is uncached. */
+	if (dram_end < 4096)
+		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+	mmu_disable_range(0, 1);
+	dcache_mmu_enable();
+
+	cbmem_initialize_empty();
+
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
+	stage_exit(entry);
+}
diff --git a/src/soc/Kconfig b/src/soc/Kconfig
index 0412919362..a36beddf5b 100644
--- a/src/soc/Kconfig
+++ b/src/soc/Kconfig
@@ -1,5 +1,6 @@
 source src/soc/intel/Kconfig
 source src/soc/nvidia/Kconfig
 source src/soc/qualcomm/Kconfig
+source src/soc/rockchip/Kconfig
 source src/soc/samsung/Kconfig
 source src/soc/ucb/Kconfig
diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc
index ab3e1662bb..80dd109422 100644
--- a/src/soc/Makefile.inc
+++ b/src/soc/Makefile.inc
@@ -4,5 +4,6 @@
 subdirs-y += intel
 subdirs-y += nvidia
 subdirs-y += qualcomm
+subdirs-y += rockchip
 subdirs-y += samsung
 subdirs-y += ucb
diff --git a/src/soc/rockchip/Kconfig b/src/soc/rockchip/Kconfig
new file mode 100644
index 0000000000..b041f89f8b
--- /dev/null
+++ b/src/soc/rockchip/Kconfig
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+source src/soc/rockchip/rk3288/Kconfig
diff --git a/src/soc/rockchip/Makefile.inc b/src/soc/rockchip/Makefile.inc
new file mode 100644
index 0000000000..aa67f5c1cf
--- /dev/null
+++ b/src/soc/rockchip/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-$(CONFIG_SOC_ROCKCHIP_RK3288) += rk3288
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
new file mode 100644
index 0000000000..51cf74ca65
--- /dev/null
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -0,0 +1,118 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOC_ROCKCHIP_RK3288
+	bool
+	default n
+	select ARCH_BOOTBLOCK_ARMV7
+	select ARCH_VERSTAGE_ARMV7
+	select ARCH_ROMSTAGE_ARMV7
+	select ARCH_RAMSTAGE_ARMV7
+	select CPU_HAS_BOOTBLOCK_INIT
+	select HAVE_MONOTONIC_TIMER
+	select HAVE_UART_MEMORY_MAPPED
+	select HAVE_UART_SPECIAL
+	select BOOTBLOCK_CONSOLE
+	select DYNAMIC_CBMEM
+	
+if SOC_ROCKCHIP_RK3288
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "soc/rockchip/rk3288/bootblock.c"
+
+# ROM image layout.
+#
+# 0x00000 Combined bootblock and ID Block
+# 0x08000 Master CBFS header.
+# 0x18000 Free for CBFS data.
+#
+# iRAM (96k) layout.
+# (Note: The BootROM will jump to 0xff704004 after loading bootblock,
+#  so the bootblock loading address must be at 0xff704004.)
+#
+# 0xFF70_0000 TTB (16KB).
+# 0xFF70_4004 Bootblock (max 16KB-4B).
+# 0xFF70_8000 ROM stage (max 40KB).
+# 0xFF71_2000 STACK (4KB).
+# 0xFF71_3000 CBFS mapping cache (20K)
+# 0xFF71_7FFF End of iRAM.
+
+config SYS_SDRAM_BASE
+	hex "SDRAM base address"
+	default 0x00000000
+
+config STACK_TOP
+	hex "STACK TOP"
+	default 0xff713000
+
+config STACK_BOTTOM
+	hex "STACK BOTTOM"
+	default 0xff712000
+
+config BOOTBLOCK_BASE
+	hex
+	default 0xff704004
+
+config ROMSTAGE_BASE
+	hex "ROM STAGE BASE"
+	default 0xff708000
+
+config RAMSTAGE_BASE
+	hex "RAMSTAGE BASE"
+	default 0x00200000
+
+config BOOTBLOCK_ROM_OFFSET
+	hex
+	default 0x0
+
+config CBFS_HEADER_ROM_OFFSET
+	hex
+	default 0x0008000
+
+config CBFS_ROM_OFFSET
+	hex
+	default 0x0018000
+
+config CBFS_SRAM_CACHE_ADDRESS
+	hex "sram memory address to put CBFS cache data"
+	default 0xff713000
+
+config CBFS_SRAM_CACHE_SIZE
+	hex "size of CBFS cache data"
+	default 0x00005000
+
+config CBFS_DRAM_CACHE_ADDRESS
+	hex "dram memory address to put CBFS cache data"
+	default 0x01000000
+
+config CBFS_DRAM_CACHE_SIZE
+	hex "size of CBFS cache data"
+	default 0x00100000
+
+config TTB_BUFFER
+	hex "memory address of the TTB buffer"
+	default 0xff700000
+
+config CONSOLE_SERIAL_UART_ADDRESS
+	hex
+	depends on CONSOLE_SERIAL_UART
+	default 0xFF690000
+
+endif
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
new file mode 100644
index 0000000000..50a1bbfcf6
--- /dev/null
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#bootblock-y += bootblock.c
+bootblock-y += cbmem.c
+bootblock-y += timer.c
+bootblock-y += monotonic_timer.c
+bootblock-y += media.c
+ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
+bootblock-$(CONFIG_DRIVERS_UART) += uart.c
+endif
+
+romstage-y += cbmem.c
+romstage-y += timer.c
+romstage-y += monotonic_timer.c
+romstage-y += media.c
+romstage-$(CONFIG_DRIVERS_UART) += uart.c
+
+ramstage-y += cbmem.c
+ramstage-y += timer.c
+ramstage-y += monotonic_timer.c
+ramstage-y += media.c
+ramstage-$(CONFIG_DRIVERS_UART) += uart.c
diff --git a/src/soc/rockchip/rk3288/addressmap.h b/src/soc/rockchip/rk3288/addressmap.h
new file mode 100644
index 0000000000..865e3c2ed1
--- /dev/null
+++ b/src/soc/rockchip/rk3288/addressmap.h
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__
+#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__
+
+#define SDMMC1_BASE		0xFF0C0000
+#define SDMMC0_BASE		0xFF0D0000
+#define EMMC_BASE		0xFF0F0000
+#define SARADC_BASE		0xFF100000
+
+#define SPI0_BASE		0xFF110000
+#define SPI1_BASE		0xFF120000
+#define SPI2_BASE		0xFF130000
+
+#define I2C1_BASE		0xFF140000
+#define I2C3_BASE		0xFF150000
+#define I2C4_BASE		0xFF160000
+#define I2C5_BASE		0xFF170000
+#define UART0_BASE		0xFF180000
+#define UART1_BASE		0xFF190000
+#define DMAC_PERI_BASE		0xFF250000
+
+#define NANDC0_BASE		0xFF400000
+#define NANDC1_BASE		0xFF410000
+
+#define USB_HOST0_EHCI_BASE	0xFF500000
+#define USB_HOST0_OHCI_BASE	0xFF520000
+#define USB_HOST1_BASE		0xFF540000
+#define USB_OTG_BASE		0xFF580000
+
+#define DMAC_BUS_BASE		0xFF600000
+
+#define DDR_PCTL0_BASE		0xFF610000
+#define DDR_PCTL1_BASE		0xFF630000
+#define DDR_PUBL0_BASE		0xFF620000
+#define DDR_PUBL1_BASE		0xFF640000
+
+#define I2C0_BASE		0xFF650000
+#define I2C2_BASE		0xFF660000
+#define DW_PWM0123_BASE		0xFF670000
+#define RK_PWM0123_BASE		0xFF680000
+#define UART2_BASE		0xFF690000
+#define TIMER0_BASE		0xFF6B0000
+
+#define SRAM_BASE		0xFF700000
+#define PMU_BASE		0xFF730000
+#define GRF_SECURE_BASE		0xFF740000
+#define GPIO0_BASE		0xFF750000
+#define CRU_BASE		0xFF760000
+#define GRF_BASE		0xFF770000
+#define GPIO1_BASE		0xFF780000
+#define GPIO2_BASE		0xFF790000
+#define GPIO3_BASE		0xFF7A0000
+#define GPIO4_BASE		0xFF7B0000
+#define GPIO5_BASE		0xFF7C0000
+#define GPIO6_BASE		0xFF7D0000
+#define GPIO7_BASE		0xFF7E0000
+#define GPIO8_BASE		0xFF7F0000
+
+#define TIMER6_BASE		0xFF810000
+#define TIMER7_BASE		0xFF810020
+
+#define VOP_BIG_BASE		0xFF930000
+#define HDMI_TX_BASE		0xFF980000
+#define DMACS_BUS_BASE		0xFFB20000
+
+#define	SERVICE_CORE_BASE	0xFFA80000
+#define	SERVICE_DMA_BASE	0xFFA90000
+#define	SERVICE_GPU_BASE	0xFFAA0000
+#define	SERVICE_PERI_BASE	0xFFAB0000
+#define	SERVICE_BUS_BASE	0xFFAC0000
+#define	SERVICE_VIO_BASE	0xFFAD0000
+#define	SERVICE_VPU_BASE	0xFFAE0000
+#define	SERVICE_HEVC_BASE	0xFFAF0000
+
+#define EFUSE_BASE		0xFFB40000
+
+#define CORE_GICD_BASE		0xFFC01000
+#define CORE_GICC_BASE		0xFFC02000
+#define CPU_AXI_BUS_BASE	0xFFE00000
+
+#define BOOT_ROM_BASE		0xFFFF0000
+#define BOOT_ROM_CHIP_VER	(BOOT_ROM+0x27F0)
+
+#endif	/* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
new file mode 100644
index 0000000000..9adf6ac242
--- /dev/null
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/cache.h>
+#include <bootblock_common.h>
+#include "timer.h"
+
+static void bootblock_cpu_init(void)
+{
+	rk3288_init_timer();
+}
diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c
new file mode 100644
index 0000000000..b29c87aaa5
--- /dev/null
+++ b/src/soc/rockchip/rk3288/cbmem.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <cbmem.h>
+
+#define FB_SIZE_MB	4
+void *cbmem_top(void)
+{
+	return (void *)(CONFIG_SYS_SDRAM_BASE +
+			(CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)*MiB);
+}
+
diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c
new file mode 100644
index 0000000000..75713eba7c
--- /dev/null
+++ b/src/soc/rockchip/rk3288/media.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <string.h>
+#include <console/console.h>
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+	return 0;
+}
diff --git a/src/soc/rockchip/rk3288/monotonic_timer.c b/src/soc/rockchip/rk3288/monotonic_timer.c
new file mode 100644
index 0000000000..d33ed6858c
--- /dev/null
+++ b/src/soc/rockchip/rk3288/monotonic_timer.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <timer.h>
+#include <arch/io.h>
+#include "addressmap.h"
+#include "timer.h"
+
+static uint64_t timer_raw_value(void)
+{
+	uint64_t value0;
+	uint64_t value1;
+
+	value0 = (uint64_t)read32(&timer7_ptr->timer_curr_value0);
+	value1 = (uint64_t)read32(&timer7_ptr->timer_curr_value1);
+	value0 = value0 | value1<<32;
+	return value0;
+}
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+	mono_time_set_usecs(mt, timer_raw_value() / clocks_per_usec);
+}
diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c
new file mode 100644
index 0000000000..3a2c34d341
--- /dev/null
+++ b/src/soc/rockchip/rk3288/timer.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <timer.h>
+#include <delay.h>
+#include <arch/io.h>
+#include "timer.h"
+
+void init_timer(void)
+{
+}
+
+void rk3288_init_timer(void)
+{
+	write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0);
+	write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1);
+	write32(1, &timer7_ptr->timer_ctrl_reg);
+}
+
+/* delay x useconds */
+void udelay(unsigned usec)
+{
+	struct mono_time current, end;
+
+	timer_monotonic_get(&current);
+	end = current;
+	mono_time_add_usecs(&end, usec);
+
+	if (mono_time_after(&current, &end)) {
+		printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n",
+				usec);
+		/* There's not much we can do if usec is too big. Use a long,
+		 * paranoid delay value and hope for the best... */
+		end = current;
+		mono_time_add_usecs(&end, USECS_PER_SEC);
+	}
+
+	while (mono_time_before(&current, &end))
+		timer_monotonic_get(&current);
+}
+
diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h
new file mode 100644
index 0000000000..8c72a4f373
--- /dev/null
+++ b/src/soc/rockchip/rk3288/timer.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ROCKCHIP_RK3288_TIMER_H__
+#define __ROCKCHIP_RK3288_TIMER_H__
+
+#include "addressmap.h"
+
+#define SYS_CLK_FREQ	24000000
+static const uint32_t clocks_per_usec = SYS_CLK_FREQ/1000000;
+
+struct rk3288_timer {
+	u32 timer_load_count0;
+	u32 timer_load_count1;
+	u32 timer_curr_value0;
+	u32 timer_curr_value1;
+	u32 timer_ctrl_reg;
+	u32 timer_int_status;
+};
+
+static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+void rk3288_init_timer(void);
+
+#endif	/* __ROCKCHIP_RK3288_TIMER_H__ */
diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c
new file mode 100644
index 0000000000..60b14a3209
--- /dev/null
+++ b/src/soc/rockchip/rk3288/uart.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>	/* for __console definition */
+#include <stdint.h>
+#include <drivers/uart/uart8250reg.h>
+
+/*
+ * TODO: Use DRIVERS_UART_8250MEM driver instead.
+ * There is an issue in the IO call functions where x86 and ARM
+ * ordering is reversed. This 8250MEM driver uses the x86 convention.
+ * This driver can be replaced once the IO calls are sorted.
+ */
+
+struct rk3288_uart {
+	union {
+		uint32_t thr; /* Transmit holding register. */
+		uint32_t rbr; /* Receive buffer register. */
+		uint32_t dll; /* Divisor latch lsb. */
+	};
+	union {
+		uint32_t ier; /* Interrupt enable register. */
+		uint32_t dlm; /* Divisor latch msb. */
+	};
+	union {
+		uint32_t iir; /* Interrupt identification register. */
+		uint32_t fcr; /* FIFO control register. */
+	};
+	uint32_t lcr; /* Line control register. */
+	uint32_t mcr; /* Modem control register. */
+	uint32_t lsr; /* Line status register. */
+	uint32_t msr; /* Modem status register. */
+	uint32_t scr;
+	uint32_t reserved1[(0x30 - 0x20) / 4];
+	uint32_t srbr[(0x70 - 0x30) / 4];
+	uint32_t far;
+	uint32_t tfr;
+	uint32_t rfw;
+	uint32_t usr;
+	uint32_t tfl;
+	uint32_t rfl;
+	uint32_t srr;
+	uint32_t srts;
+	uint32_t sbcr;
+	uint32_t sdmam;
+	uint32_t sfe;
+	uint32_t srt;
+	uint32_t stet;
+	uint32_t htx;
+	uint32_t dmasa;
+	uint32_t reserver2[(0xf4 - 0xac) / 4];
+	uint32_t cpr;
+	uint32_t ucv;
+	uint32_t ctr;
+} __attribute__ ((packed));
+
+
+static struct rk3288_uart * const uart_ptr =
+	(void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+
+static void rk3288_uart_tx_flush(void);
+static int rk3288_uart_tst_byte(void);
+
+static void rk3288_uart_init(void)
+{
+	/* FIXME: Use a hardcoded divisor for now.
+	 * uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(),
+	 *	uart_platform_refclk(), 16)
+	 */
+	const unsigned divisor = 13;
+	const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
+
+	rk3288_uart_tx_flush();
+
+	// Disable interrupts.
+	writel(0, &uart_ptr->ier);
+	// Force DTR and RTS to high.
+	writel(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+	// Set line configuration, access divisor latches.
+	writel(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+	// Set the divisor.
+	writel(divisor & 0xff, &uart_ptr->dll);
+	writel((divisor >> 8) & 0xff, &uart_ptr->dlm);
+	// Hide the divisor latches.
+	writel(line_config, &uart_ptr->lcr);
+	// Enable FIFOs, and clear receive and transmit.
+	writel(UART8250_FCR_FIFO_EN |
+		UART8250_FCR_CLEAR_RCVR |
+		UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+}
+
+static void rk3288_uart_tx_byte(unsigned char data)
+{
+	while (!(readl(&uart_ptr->lsr) & UART8250_LSR_THRE));
+	writel(data, &uart_ptr->thr);
+}
+
+static void rk3288_uart_tx_flush(void)
+{
+	while (!(readl(&uart_ptr->lsr) & UART8250_LSR_TEMT));
+}
+
+static unsigned char rk3288_uart_rx_byte(void)
+{
+	if (!rk3288_uart_tst_byte())
+		return 0;
+	return readl(&uart_ptr->rbr);
+}
+
+static int rk3288_uart_tst_byte(void)
+{
+	return (readl(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
+}
+
+
+
+void uart_init(int idx)
+{
+	rk3288_uart_init();
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+	return rk3288_uart_rx_byte();
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	rk3288_uart_tx_byte(data);
+}
+
+void uart_tx_flush(int idx)
+{
+	rk3288_uart_tx_flush();
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+	struct lb_serial serial;
+	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+	serial.baud = default_baudrate();
+	lb_add_serial(&serial, data);
+
+	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif