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| author | Subrata Banik <subratabanik@google.com> | 2024-08-08 14:46:35 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-08-09 09:24:30 +0000 |
| commit | ab1d04a0c4d24073eb5bb324260f3fe78b992fea (patch) | |
| tree | 29e40531f7a67e37124c162ed8e08d0b1048d36a | |
| parent | c84ff28ac534739bcc46d248639f32e6cc9c17c7 (diff) | |
mb/google/fatcat: Add support for soldered-down memory
This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.
* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
* `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
* `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.
BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.
Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
| -rw-r--r-- | src/mainboard/google/fatcat/Kconfig | 6 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/Makefile.mk | 2 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/spd/Makefile.mk | 6 |
3 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 2c6ddd21f2..42a839c188 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_FATCAT select BOARD_GOOGLE_FATCAT_COMMON select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS + select MEMORY_SOLDERDOWN select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_METEORLAKE_U_H select SYSTEM_TYPE_LAPTOP @@ -85,6 +86,11 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Fatcat" if BOARD_GOOGLE_FATCAT +config MEMORY_SOLDERDOWN + def_bool n + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select HAVE_SPD_IN_CBFS + # FIXME: update as per board schematics config TPM_TIS_ACPI_INTERRUPT int diff --git a/src/mainboard/google/fatcat/Makefile.mk b/src/mainboard/google/fatcat/Makefile.mk index 11098e2631..8c60c591aa 100644 --- a/src/mainboard/google/fatcat/Makefile.mk +++ b/src/mainboard/google/fatcat/Makefile.mk @@ -17,6 +17,8 @@ BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR)) subdirs-y += variants/baseboard/$(BASEBOARD_DIR) subdirs-y += variants/$(VARIANT_DIR) +subdirs-y += variants/$(VARIANT_DIR)/memory +subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include diff --git a/src/mainboard/google/fatcat/spd/Makefile.mk b/src/mainboard/google/fatcat/spd/Makefile.mk new file mode 100644 index 0000000000..be4d98bd1d --- /dev/null +++ b/src/mainboard/google/fatcat/spd/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## + +ifneq ($(SPD_SOURCES),) +LIB_SPD_DEPS := $(SPD_SOURCES) +endif |