diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-15 06:08:15 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 00:19:08 +0200 |
| commit | a969ed34dbaebc595e298f60810669f0e8a3bcd2 (patch) | |
| tree | f55750965fb4f87db09d73e4571f28eb20a59964 | |
| parent | 465eff61f4f0f730476aa7afe8819f1e6b118068 (diff) | |
Move definitions of HIGH_MEMORY_SAVE
This is more of ACPI S3 resume and x86 definition than CBMEM.
Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15190
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/arch/x86/include/arch/acpi.h | 10 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/include/cbmem.h | 8 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t400/romstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x200/romstage.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 1 |
9 files changed, 17 insertions, 8 deletions
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 276ca5210d..5674c3a240 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -24,6 +24,14 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ + ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#else +#define HIGH_MEMORY_SAVE 0 +#endif + +#ifndef __ASSEMBLER__ #include <stdint.h> #include <rules.h> #include <commonlib/helpers.h> @@ -643,4 +651,6 @@ static inline uintptr_t acpi_align_current(uintptr_t current) return ALIGN(current, 16); } +#endif /* __ASSEMBLER__ */ + #endif /* __ASM_ACPI_H */ diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 492728dcf9..5f486f2fea 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9c08aa16ba..b8ce5d6d43 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -24,6 +24,7 @@ #include <halt.h> #include <lib.h> #include <timestamp.h> +#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pci_def.h> diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index eef12b7e8d..358ba75e04 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -18,6 +18,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cbmem.h> +#include <arch/acpi.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 524bfb5748..2182ce7a46 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -19,14 +19,6 @@ #include <commonlib/cbmem_id.h> #include <rules.h> - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) -#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) -#else -#define HIGH_MEMORY_SAVE 0 -#endif - /* Delegation of resume backup memory so we don't have to * (slowly) handle backing up OS memory in romstage.c */ diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 486b738e51..16676faa02 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 86a973fff1..91500f4774 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 475e88a4e5..ab814e8e3c 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <stdlib.h> #include <console/console.h> +#include <arch/acpi.h> #include <arch/io.h> #include <device/pci_def.h> #include <cbmem.h> diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b8daedc133..779f29befd 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -18,6 +18,7 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <device/pci_def.h> #include <elog.h> #include <cbmem.h> |