diff options
author | Nico Huber <nico.h@gmx.de> | 2021-03-06 14:13:58 +0100 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2021-03-12 23:44:49 +0000 |
commit | a768deae7346c5de740723331e3eb5ee04746bfe (patch) | |
tree | d96270ac5f62f957f2848291676954d2611898b7 | |
parent | 2d24146aef39ef5a6b1d061a81c8c9e333886b5c (diff) |
device: Give `pci_ops.set_L1_ss_latency` a proper name
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`.
TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.
Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/device/pciexp_device.c | 4 | ||||
-rw-r--r-- | src/include/device/pci.h | 2 | ||||
-rw-r--r-- | src/soc/intel/broadwell/pch/pcie.c | 4 | ||||
-rw-r--r-- | src/soc/intel/common/block/pcie/pcie.c | 4 |
4 files changed, 7 insertions, 7 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 8d4bb9849d..3153e0eb37 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -132,8 +132,8 @@ static void pciexp_config_max_latency(struct device *root, struct device *dev) unsigned int cap; cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID); if ((cap) && (root->ops->ops_pci != NULL) && - (root->ops->ops_pci->set_L1_ss_latency != NULL)) - root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4); + (root->ops->ops_pci->set_ltr_max_latencies != NULL)) + root->ops->ops_pci->set_ltr_max_latencies(dev, cap + 4); } static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 045eec1aa6..e80cb22907 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -31,7 +31,7 @@ struct pci_operations { /* set the Subsystem IDs for the PCI device */ void (*set_subsystem)(struct device *dev, unsigned int vendor, unsigned int device); - void (*set_L1_ss_latency)(struct device *dev, unsigned int off); + void (*set_ltr_max_latencies)(struct device *dev, unsigned int off); }; struct pci_driver { diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 7f16cb4d2c..05619f8023 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -609,7 +609,7 @@ static void pch_pcie_enable(struct device *dev) root_port_commit_config(); } -static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) +static void pcie_set_ltr_max_latencies(struct device *dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ pci_write_config32(dev, off, @@ -619,7 +619,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) static struct pci_operations pcie_ops = { .set_subsystem = pci_dev_set_subsystem, - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_ltr_max_latencies = pcie_set_ltr_max_latencies, }; static struct device_operations device_ops = { diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 4f5687fd5f..346c0ff225 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -45,7 +45,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, PCI_SEC_STATUS, reg16); } -static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) +static void pcie_set_ltr_max_latencies(struct device *dev, unsigned int offset) { /* Set max snoop and non-snoop latency for the SOC */ pci_write_config32(dev, offset, @@ -54,7 +54,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) } static struct pci_operations pcie_ops = { - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_ltr_max_latencies = pcie_set_ltr_max_latencies, .set_subsystem = pci_dev_set_subsystem, }; |