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authorNick Vaccaro <nvaccaro@google.com>2021-10-01 13:12:59 -0700
committerNick Vaccaro <nvaccaro@google.com>2021-10-04 17:12:48 +0000
commita62b41819ceda4108b3a97cf72f55fc470347d58 (patch)
tree43d4c2ee7badea8dcac7388d6671dbe2a0f5a211
parent56da0b79ad6f3a96f5c14405d8622b7ed10aa1f2 (diff)
coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat
-rw-r--r--payloads/libpayload/include/coreboot_tables.h22
-rw-r--r--payloads/libpayload/include/sysinfo.h2
-rw-r--r--payloads/libpayload/libc/coreboot.c8
-rw-r--r--src/commonlib/include/commonlib/cbmem_id.h4
-rw-r--r--src/commonlib/include/commonlib/coreboot_tables.h18
-rw-r--r--src/lib/coreboot_table.c1
6 files changed, 54 insertions, 1 deletions
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 91f848654f..a841e0326f 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -82,6 +82,7 @@ enum {
CB_TAG_SMMSTOREV2 = 0x0039,
CB_TAG_BOARD_CONFIG = 0x0040,
CB_TAG_ACPI_CNVS = 0x0041,
+ CB_TAG_TYPE_C_INFO = 0x0042,
CB_TAG_CMOS_OPTION_TABLE = 0x00c8,
CB_TAG_OPTION = 0x00c9,
CB_TAG_OPTION_ENUM = 0x00ca,
@@ -142,6 +143,27 @@ struct cb_mainboard {
u8 strings[0];
};
+struct type_c_port_info {
+ /*
+ * usb2_port_number and usb3_port_number are expected to be
+ * the port numbers as seen by the USB controller in the SoC.
+ */
+ uint8_t usb2_port_number;
+ uint8_t usb3_port_number;
+
+ /*
+ * Valid sbu_orientation and data_orientation values will be of
+ * type enum type_c_orienation.
+ */
+ uint8_t sbu_orientation;
+ uint8_t data_orientation;
+};
+
+struct type_c_info {
+ u32 port_count;
+ struct type_c_port_info port_info[0];
+};
+
struct cb_string {
u32 tag;
u32 size;
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 26dece7ce1..b34476d25e 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -148,6 +148,8 @@ struct sysinfo_t {
#if CONFIG(LP_PCI)
struct pci_access pacc;
#endif
+ /* USB Type-C Port Configuration Info */
+ uintptr_t type_c_info;
};
extern struct sysinfo_t lib_sysinfo;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 269275d604..bd1041166e 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -246,6 +246,11 @@ static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info)
info->fmap_cache = get_cbmem_addr(ptr);
}
+static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info)
+{
+ info->type_c_info = get_cbmem_addr(ptr);
+}
+
#if CONFIG(LP_TIMER_RDTSC)
static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
{
@@ -420,6 +425,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_FMAP:
cb_parse_fmap_cache(ptr, info);
break;
+ case CB_TAG_TYPE_C_INFO:
+ cb_parse_type_c_info(ptr, info);
+ break;
default:
cb_parse_arch_specific(rec, info);
break;
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
index d251a4e190..a9cf7bdcf6 100644
--- a/src/commonlib/include/commonlib/cbmem_id.h
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -78,6 +78,7 @@
#define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346
#define CBMEM_ID_FSP_LOGO 0x4c4f474f
#define CBMEM_ID_SMM_COMBUFFER 0x53534d32
+#define CBMEM_ID_TYPE_C_INFO 0x54595045
#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
@@ -145,5 +146,6 @@
{ CBMEM_ID_ROM3, "VGA ROM #3 "}, \
{ CBMEM_ID_FMAP, "FMAP "}, \
{ CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \
- { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}
+ { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \
+ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}
#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index fd7461d584..ab8da7bf8e 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -84,6 +84,7 @@ enum {
LB_TAG_TPM_PPI_HANDOFF = 0x003a,
LB_TAG_BOARD_CONFIG = 0x0040,
LB_TAG_ACPI_CNVS = 0x0041,
+ LB_TAG_TYPE_C_INFO = 0x0042,
/* The following options are CMOS-related */
LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
LB_TAG_OPTION = 0x00c9,
@@ -421,6 +422,23 @@ struct lb_mmc_info {
int32_t early_cmd1_status;
};
+/*
+ * USB Type-C Port Information
+ * This record contains board-specific type-c port information.
+ * There will be one record per type-C port.
+ */
+struct type_c_port_info {
+ uint8_t usb2_port_number;
+ uint8_t usb3_port_number;
+ uint8_t sbu_orientation;
+ uint8_t data_orientation;
+};
+
+struct type_c_info {
+ uint32_t port_count;
+ struct type_c_port_info port_info[0];
+};
+
struct lb_macs {
uint32_t tag;
uint32_t size;
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 27f5315c23..d0cba80dcc 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -252,6 +252,7 @@ static void add_cbmem_pointers(struct lb_header *header)
{CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG},
{CBMEM_ID_FMAP, LB_TAG_FMAP},
{CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF},
+ {CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO},
};
int i;
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-31 14:09:46 +0000