diff options
| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-11-03 13:24:29 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-03 13:24:29 +0000 |
| commit | a215b0f0be2116b77192d6a3ec06a5616207432a (patch) | |
| tree | 34b260987d1d695ff972fadf01e2a3a0cf7a9f65 | |
| parent | e98db798c9cbf30dd982fdacbaf0b860c1e42a48 (diff) | |
Remove some unused code from gx2/raminit.c.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index a895ea8fee..2c028e931c 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -460,12 +460,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) msr.lo &= ~0xC0; msr.lo |= 0x0; /* set refresh to 4SDRAM clocks */ wrmsr(msrnum, msr); - - /* Memory Interleave: Set HOI here otherwise default is LOI */ - /* msrnum = MC_CF8F_DATA; - msr = rdmsr(msrnum); - msr.hi |= CF8F_UPPER_HOI_LOI_SET; - wrmsr(msrnum, msr); */ } static void sdram_set_spd_registers(const struct mem_controller *ctrl) |