diff options
| author | Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> | 2020-12-03 18:47:04 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-08 19:38:35 +0000 |
| commit | 9cce83c58e3ad6f1b9a8f29f3c6831c696cb5622 (patch) | |
| tree | ae8c55be90e58b19722e1b26b1b46685e1ebb58e | |
| parent | e9eecc902fede4790ac0592493e2d930b39ff448 (diff) | |
mb/google/volteer/var/voxel: Update DPTF parameters
remove TCC offset setting in overridetree.cb,
use default setting(# TCC of 90) in baseboard.
BUG=b:174547185
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/volteer/variants/voxel/overridetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 9c4aa47d2f..2dd15669fe 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "tcc_offset" = "5" # TCC of 95 register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 18, |