diff options
author | Angel Pons <th3fanbus@gmail.com> | 2021-10-15 15:42:14 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-29 15:01:13 +0000 |
commit | 9c30a2944beaa325750fcdfaab1129871407d0b9 (patch) | |
tree | b65976f7129f7206982347c4e12ab347a03bb3cf | |
parent | 047835aba7e0dea609590797c6ce72c331f94536 (diff) |
mb/prodrive/hermes: Enable LTR for all PCIe ports
Set the `PcieRpLtrEnable` option to enable the LTR capability on all PCH
PCIe root ports.
TEST=Verify LTR capability enabled in `DevCap2` using `lspci -vv`
Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58326
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index a57931ba94..8faf016e7c 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -198,34 +198,42 @@ chip soc/intel/cannonlake end device pci 1c.4 on # PCIe root port 5 (PHY 3) register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" end device pci 1c.5 on # PCIe root port 6 (PHY 4) register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" end device pci 1c.6 on # PCIe root port 7 (PHY 2) register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" end device pci 1c.7 on # PCIe root port 8 (PHY 1) register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" end device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" end device pci 1d.5 on # PCIe root port 14 (PHY 0) register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" end device pci 1d.6 on # PCIe root port 15 (BMC) device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2500 VGA end register "PcieRpEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "1" register "PcieRpSlotImplemented[14]" = "1" end device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) # Disabled when CNVi is present register "PcieRpEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "1" register "PcieRpSlotImplemented[15]" = "1" end device pci 1e.0 on end # UART #0 |