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authorMAULIK V VAGHELA <maulik.v.vaghela@intel.com>2021-10-13 11:52:17 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-10-26 05:47:07 +0000
commit9a7fbbc98e8610a0a5314470edd8d5dafe676a06 (patch)
tree6be1494d682b5bd84b8bdded8c2a898f5cd89322
parent1a950d6466473e0f5047cff33929c7da1b3f6787 (diff)
soc/intel/adl: Skip sending MBP HOB to save boot time
MBP Hob is being generated by FSP after getting data from ME. coreboot does not consume this HOB and FSP provides an option for bootloader to skip generation of MBP HOB. This will help in saving ~14 ms of boot time. Here is the data from Brya P1 Board: Before: 955 returning from FspSiliconInit 879,432 (99,156) After: 955 returning from FspSiliconInit 1,177,513 (84,506) BUG=b:188577893 BRANCH=None TEST=No functional impact on Brya system and boot time is reduced with this patch. Change-Id: Ibb64e4d0f4ae7212defb6704b05a78e754f75cd7 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58289 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 698cff67ce..be71a02c0a 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -203,6 +203,9 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
/* Skip GPIO configuration from FSP */
m_cfg->GpioOverride = 0x1;
+
+ /* Skip generation of MBP HOB from FSP. coreboot doesn't consume it */
+ m_cfg->SkipMbpHob = 1;
}
static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,