diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-05 00:14:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-10 20:44:45 +0000 |
| commit | 9a6bc07cc26a93c434bc8dac86cf13c0edef09a8 (patch) | |
| tree | 683aac37228419a30332a6207b609e7ef9e93cb7 | |
| parent | e1a27f2e491b666f69fb198546370741e6125eda (diff) | |
soc/amd/cezanne: select common APOB NV cache code
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index d491da4df7..290fc229a6 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -31,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index b35e6a56af..17c7d755bf 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <arch/cpu.h> #include <console/console.h> @@ -13,6 +14,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); + mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; @@ -31,6 +34,7 @@ asmlinkage void car_stage_entry(void) post_code(0x41); fsp_memory_init(acpi_is_wakeup_s3()); + soc_update_apob_cache(); /* Fixup settings FSP-M should not be changing */ fch_disable_legacy_dma_io(); |