diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2021-05-11 16:41:37 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-05-14 23:00:21 +0000 |
| commit | 97b608feed7fddf40a586ca3600b35bc877aa341 (patch) | |
| tree | 56612ae3e4fafa7435fb74a06c3682a904b7c954 | |
| parent | 4b3e06edf2b7c2d99912038589764d551bc00c6f (diff) | |
mb/google/volteer: Configure TCSS OC pins
TCSS OC pins have not been correctly configured for volteer.
This patch fills the value from devicetree to correct the OC pins
mapping.
BUG=b:184660529
BRANCH=None
TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and
verify CpuUsb3OverCurrentPin UPDs get set correctly.
Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index fdac104755..0f440f576f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -111,6 +111,9 @@ chip soc/intel/tigerlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" |