acpi: correct the processor devices scope

The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.

Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.

TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

45 files changed, 189 insertions, 74 deletions

diff --git a/src/cpu/amd/agesa/family14/acpi/cpu.asl b/src/cpu/amd/agesa/family14/acpi/cpu.asl
index 98b0193c77..b10fd56120 100644
--- a/src/cpu/amd/agesa/family14/acpi/cpu.asl
+++ b/src/cpu/amd/agesa/family14/acpi/cpu.asl
@@ -15,7 +15,7 @@
  * Processor Object
  *
  */
-Scope (\_PR) {		/* define processor scope */
+Scope (\_SB) {		/* define processor scope */
 
 	Device (C000) {
 	Name (_HID, "ACPI0007")
@@ -26,4 +26,4 @@ Scope (\_PR) {		/* define processor scope */
 	Name (_HID, "ACPI0007")
 	Name (_UID, 1)
 	}
-} /* End _PR scope */
+} /* End _SB scope */
diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl
index 68e6e97bf3..19ec12b1ec 100644
--- a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl
+++ b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl
@@ -15,7 +15,7 @@
  * Processor Object
  *
  */
-Scope (\_PR) {	/* define processor scope */
+Scope (\_SB) {	/* define processor scope */
 
 	Device (P000) {
 	Name(_HID, "ACPI0007")
@@ -56,4 +56,4 @@ Scope (\_PR) {	/* define processor scope */
 	Name(_HID, "ACPI0007")
 	Name(_UID, 7)
 	}
-} /* End _PR scope */
+} /* End _SB scope */
diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl
index 37eb58abc0..48505ebddf 100644
--- a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl
+++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl
@@ -15,7 +15,7 @@
  * Processor Object
  *
  */
-Scope (\_PR) {/* define processor scope */
+Scope (\_SB) {/* define processor scope */
 	Device (P000) {
 	Name(_HID, "ACPI0007")
 	Name(_UID, 0)
@@ -55,4 +55,4 @@ Scope (\_PR) {/* define processor scope */
 	Name(_HID, "ACPI0007")
 	Name(_UID, 7)
 	}
-} /* End _PR scope */
+} /* End _SB scope */
diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl
index 68e6e97bf3..19ec12b1ec 100644
--- a/src/cpu/amd/pi/00630F01/acpi/cpu.asl
+++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl
@@ -15,7 +15,7 @@
  * Processor Object
  *
  */
-Scope (\_PR) {	/* define processor scope */
+Scope (\_SB) {	/* define processor scope */
 
 	Device (P000) {
 	Name(_HID, "ACPI0007")
@@ -56,4 +56,4 @@ Scope (\_PR) {	/* define processor scope */
 	Name(_HID, "ACPI0007")
 	Name(_UID, 7)
 	}
-} /* End _PR scope */
+} /* End _SB scope */
diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl
index 68e6e97bf3..19ec12b1ec 100644
--- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl
+++ b/src/cpu/amd/pi/00660F01/acpi/cpu.asl
@@ -15,7 +15,7 @@
  * Processor Object
  *
  */
-Scope (\_PR) {	/* define processor scope */
+Scope (\_SB) {	/* define processor scope */
 
 	Device (P000) {
 	Name(_HID, "ACPI0007")
@@ -56,4 +56,4 @@ Scope (\_PR) {	/* define processor scope */
 	Name(_HID, "ACPI0007")
 	Name(_UID, 7)
 	}
-} /* End _PR scope */
+} /* End _SB scope */
diff --git a/src/cpu/amd/pi/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl
index 68e6e97bf3..19ec12b1ec 100644
--- a/src/cpu/amd/pi/00730F01/acpi/cpu.asl
+++ b/src/cpu/amd/pi/00730F01/acpi/cpu.asl
@@ -15,7 +15,7 @@
  * Processor Object
  *
  */
-Scope (\_PR) {	/* define processor scope */
+Scope (\_SB) {	/* define processor scope */
 
 	Device (P000) {
 	Name(_HID, "ACPI0007")
@@ -56,4 +56,4 @@ Scope (\_PR) {	/* define processor scope */
 	Name(_HID, "ACPI0007")
 	Name(_UID, 7)
 	}
-} /* End _PR scope */
+} /* End _SB scope */
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index f1a49ef5c9..6ecea61936 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -39,7 +39,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl
index a7914191d0..15b241f897 100644
--- a/src/mainboard/amd/olivehill/dsdt.asl
+++ b/src/mainboard/amd/olivehill/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl
index e39ce0c836..0e45e0784d 100644
--- a/src/mainboard/amd/padmelon/dsdt.asl
+++ b/src/mainboard/amd/padmelon/dsdt.asl
@@ -37,7 +37,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl
index 14a38c23bf..459d18f05f 100644
--- a/src/mainboard/amd/parmer/dsdt.asl
+++ b/src/mainboard/amd/parmer/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
 
 	/* Describe the supported Sleep States for this Southbridge */
diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl
index c88aa64bcf..4a49f6baf2 100644
--- a/src/mainboard/amd/thatcher/acpi/cpstate.asl
+++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl
@@ -21,7 +21,7 @@
 #include <arch/acpi.h>
 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
 	{
-	Scope (\_PR) {
+	Scope (\_SB) {
 		Device (CPU0) {
 		Name (_HID, "ACPI0007")
 		Name (_UID, 0)
diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl
index 14a38c23bf..459d18f05f 100644
--- a/src/mainboard/amd/thatcher/dsdt.asl
+++ b/src/mainboard/amd/thatcher/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
 
 	/* Describe the supported Sleep States for this Southbridge */
diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl
index a7914191d0..15b241f897 100644
--- a/src/mainboard/asrock/imb-a180/dsdt.asl
+++ b/src/mainboard/asrock/imb-a180/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl
index fcae00b660..2d55f7cf58 100644
--- a/src/mainboard/asus/am1i-a/dsdt.asl
+++ b/src/mainboard/asus/am1i-a/dsdt.asl
@@ -31,7 +31,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl
index c88aa64bcf..4a49f6baf2 100644
--- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl
@@ -21,7 +21,7 @@
 #include <arch/acpi.h>
 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
 	{
-	Scope (\_PR) {
+	Scope (\_SB) {
 		Device (CPU0) {
 		Name (_HID, "ACPI0007")
 		Name (_UID, 0)
diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl
index ad9ce1bc21..f34ccc8244 100644
--- a/src/mainboard/asus/f2a85-m/dsdt.asl
+++ b/src/mainboard/asus/f2a85-m/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
 
 	/* Describe the supported Sleep States for this Southbridge */
diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl
index 938caa5a7c..c79b78649f 100644
--- a/src/mainboard/asus/p2b-ls/dsdt.asl
+++ b/src/mainboard/asus/p2b-ls/dsdt.asl
@@ -23,7 +23,7 @@
 #include <arch/acpi.h>
 DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1)
 {
-	/* \_PR scope defining the main processor is generated in SSDT. */
+	/* \_SB scope defining the main processor is generated in SSDT. */
 
 	OperationRegion(X80, SystemIO, 0x80, 1)
 	Field(X80, ByteAcc, NoLock, Preserve)
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index c67e50fd79..b52b456983 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -23,7 +23,7 @@
 #include <arch/acpi.h>
 DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1)
 {
-	/* \_PR scope defining the main processor is generated in SSDT. */
+	/* \_SB scope defining the main processor is generated in SSDT. */
 
 	OperationRegion(X80, SystemIO, 0x80, 1)
 	Field(X80, ByteAcc, NoLock, Preserve)
diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl
index a7914191d0..15b241f897 100644
--- a/src/mainboard/bap/ode_e20XX/dsdt.asl
+++ b/src/mainboard/bap/ode_e20XX/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl
index 4bf4dc8276..8440ecaa0f 100644
--- a/src/mainboard/bap/ode_e21XX/dsdt.asl
+++ b/src/mainboard/bap/ode_e21XX/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl
index a7914191d0..15b241f897 100644
--- a/src/mainboard/biostar/a68n_5200/dsdt.asl
+++ b/src/mainboard/biostar/a68n_5200/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl
index 907b2d172d..f454732858 100644
--- a/src/mainboard/biostar/am1ml/dsdt.asl
+++ b/src/mainboard/biostar/am1ml/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl
index a7914191d0..15b241f897 100644
--- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl
+++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 7e83f06710..574145f4e5 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl
index a7914191d0..15b241f897 100644
--- a/src/mainboard/hp/abm/dsdt.asl
+++ b/src/mainboard/hp/abm/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl
index 224dd14d18..7b47a7646a 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl
+++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
 
 	/* Describe the supported Sleep States for this Southbridge */
diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl
index b36a1de71d..4eb466f819 100644
--- a/src/mainboard/lenovo/g505s/dsdt.asl
+++ b/src/mainboard/lenovo/g505s/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
 
 	/* Describe the supported Sleep States for this Southbridge */
diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl
index bf166c67af..8efa56f816 100644
--- a/src/mainboard/lippert/frontrunner-af/dsdt.asl
+++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl
@@ -56,7 +56,7 @@ DefinitionBlock (
 	 * Processor Object
 	 *
 	 */
-	Scope (\_PR) {		/* define processor scope */
+	Scope (\_SB) {		/* define processor scope */
 		Device (C000) {
 		Name (_HID, "ACPI0007")
 		Name (_UID, 0)
@@ -73,7 +73,7 @@ DefinitionBlock (
 		Name (_HID, "ACPI0007")
 		Name (_UID, 3)
 		}
-	} /* End _PR scope */
+	} /* End _SB scope */
 
 	/* PIC IRQ mapping registers, C00h-C01h. */
 	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl
index cc2a48ed5e..c494d7060c 100644
--- a/src/mainboard/lippert/toucan-af/dsdt.asl
+++ b/src/mainboard/lippert/toucan-af/dsdt.asl
@@ -56,7 +56,7 @@ DefinitionBlock (
 	 * Processor Object
 	 *
 	 */
-	Scope (\_PR) {		/* define processor scope */
+	Scope (\_SB) {		/* define processor scope */
 		Device (C000) {
 		Name (_HID, "ACPI0007")
 		Name (_UID, 0)
@@ -73,7 +73,7 @@ DefinitionBlock (
 		Name (_HID, "ACPI0007")
 		Name (_UID, 3)
 		}
-	} /* End _PR scope */
+	} /* End _SB scope */
 
 	/* PIC IRQ mapping registers, C00h-C01h. */
 	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
diff --git a/src/mainboard/msi/ms7721/acpi/cpstate.asl b/src/mainboard/msi/ms7721/acpi/cpstate.asl
index c88aa64bcf..4a49f6baf2 100644
--- a/src/mainboard/msi/ms7721/acpi/cpstate.asl
+++ b/src/mainboard/msi/ms7721/acpi/cpstate.asl
@@ -21,7 +21,7 @@
 #include <arch/acpi.h>
 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
 	{
-	Scope (\_PR) {
+	Scope (\_SB) {
 		Device (CPU0) {
 		Name (_HID, "ACPI0007")
 		Name (_UID, 0)
diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl
index d10d953f8e..ceac618519 100644
--- a/src/mainboard/msi/ms7721/dsdt.asl
+++ b/src/mainboard/msi/ms7721/dsdt.asl
@@ -31,7 +31,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
 
 	/* Describe the supported Sleep States for this Southbridge */
diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl
index 9d6138a844..cbc7293e80 100644
--- a/src/mainboard/pcengines/apu2/dsdt.asl
+++ b/src/mainboard/pcengines/apu2/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 4086173d7e..1ac5a69cf9 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -710,6 +710,21 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+	unsigned int len = ssdt->length - sizeof(acpi_header_t);
+	unsigned int i;
+
+	for (i = sizeof(acpi_header_t); i < len; i++) {
+		/* Search for _PR_ scope and replace it with _SB_ */
+		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+	}
+	/* Recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
 static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
@@ -774,6 +789,9 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
+		hexdump(ssdt, ssdt->length);
+		patch_ssdt_processor_scope(ssdt);
+		hexdump(ssdt, ssdt->length);
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 642fc150e1..a62e12e772 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -449,6 +449,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
 	acpigen_pop_len();
 }
 
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+	unsigned int len = ssdt->length - sizeof(acpi_header_t);
+	unsigned int i;
+
+	for (i = sizeof(acpi_header_t); i < len; i++) {
+		/* Search for _PR_ scope and replace it with _SB_ */
+		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+	}
+	/* Recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
 static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
@@ -525,6 +540,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
+		patch_ssdt_processor_scope(ssdt);
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index fcd7ec1fe6..2cdcb58023 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -449,6 +449,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
 	acpigen_pop_len();
 }
 
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+	unsigned int len = ssdt->length - sizeof(acpi_header_t);
+	unsigned int i;
+
+	for (i = sizeof(acpi_header_t); i < len; i++) {
+		/* Search for _PR_ scope and replace it with _SB_ */
+		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+	}
+	/* Recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
 static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
@@ -525,6 +540,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
+		patch_ssdt_processor_scope(ssdt);
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index 28502b0017..e90848a36b 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -447,6 +447,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
 	acpigen_pop_len();
 }
 
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+	unsigned int len = ssdt->length - sizeof(acpi_header_t);
+	unsigned int i;
+
+	for (i = sizeof(acpi_header_t); i < len; i++) {
+		/* Search for _PR_ scope and replace it with _SB_ */
+		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+	}
+	/* Recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
 static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
@@ -521,6 +536,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
+		patch_ssdt_processor_scope(ssdt);
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 0a1b0ba1a4..200508617c 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -435,6 +435,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
 	acpigen_pop_len();
 }
 
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+	unsigned int len = ssdt->length - sizeof(acpi_header_t);
+	unsigned int i;
+
+	for (i = sizeof(acpi_header_t); i < len; i++) {
+		/* Search for _PR_ scope and replace it with _SB_ */
+		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+	}
+	/* Recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
 static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
@@ -511,6 +526,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
+		patch_ssdt_processor_scope(ssdt);
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index c87d8fffba..f611bd6e3e 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -671,6 +671,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
 	acpigen_pop_len();
 }
 
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+	unsigned int len = ssdt->length - sizeof(acpi_header_t);
+	unsigned int i;
+
+	for (i = sizeof(acpi_header_t); i < len; i++) {
+		/* Search for _PR_ scope and replace it with _SB_ */
+		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+	}
+	/* Recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
 static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
@@ -741,6 +756,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
+		patch_ssdt_processor_scope(ssdt);
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index e8bbf57fab..8ee7c97b6c 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -236,13 +236,13 @@ void generate_cpu_entries(struct device *device)
 	int cores, cpu;
 
 	cores = get_cpu_count();
-	printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
+	printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
 
-	/* Generate BSP \_PR.P000 */
+	/* Generate BSP \_SB.P000 */
 	acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
 	acpigen_pop_len();
 
-	/* Generate AP \_PR.Pxxx */
+	/* Generate AP \_SB.Pxxx */
 	for (cpu = 1; cpu < cores; cpu++) {
 		acpigen_write_processor(cpu, 0, 0);
 		acpigen_pop_len();
diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl
index 59ac62e1ec..587dbea18c 100644
--- a/src/soc/amd/picasso/acpi/cpu.asl
+++ b/src/soc/amd/picasso/acpi/cpu.asl
@@ -21,14 +21,14 @@ Method (PNOT)
  * Processor Object
  */
 /* These devices are created at runtime */
-External (\_PR.P000, DeviceObj)
-External (\_PR.P001, DeviceObj)
-External (\_PR.P002, DeviceObj)
-External (\_PR.P003, DeviceObj)
-External (\_PR.P004, DeviceObj)
-External (\_PR.P005, DeviceObj)
-External (\_PR.P006, DeviceObj)
-External (\_PR.P007, DeviceObj)
+External (\_SB.P000, DeviceObj)
+External (\_SB.P001, DeviceObj)
+External (\_SB.P002, DeviceObj)
+External (\_SB.P003, DeviceObj)
+External (\_SB.P004, DeviceObj)
+External (\_SB.P005, DeviceObj)
+External (\_SB.P006, DeviceObj)
+External (\_SB.P007, DeviceObj)
 
 /* Return a package containing enabled processor entries */
 Method (PPKG)
@@ -36,13 +36,13 @@ Method (PPKG)
 	If (LGreaterEqual (\PCNT, 2)) {
 		Return (Package ()
 		{
-			\_PR.P000,
-			\_PR.P001
+			\_SB.P000,
+			\_SB.P001
 		})
 	} Else {
 		Return (Package ()
 		{
-			\_PR.P000
+			\_SB.P000
 		})
 	}
 }
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 1894bea418..61c7f36c07 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -367,7 +367,7 @@ static void sb_init_acpi_ports(void)
 	pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
 	pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
 
-	/* CpuControl is in \_PR.CP00, 6 bytes */
+	/* CpuControl is in \_SB.CP00, 6 bytes */
 	cst_addr.hi = 0;
 	cst_addr.lo = ACPI_CPU_CONTROL;
 	wrmsr(CSTATE_BASE_REG, cst_addr);
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 01849b85a0..f59aeb504a 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -241,13 +241,13 @@ void generate_cpu_entries(struct device *device)
 	cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
 	cores++; /* number of cores is CmpCap+1 */
 
-	printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
+	printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
 
-	/* Generate BSP \_PR.P000 */
+	/* Generate BSP \_SB.P000 */
 	acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
 	acpigen_pop_len();
 
-	/* Generate AP \_PR.Pxxx */
+	/* Generate AP \_SB.Pxxx */
 	for (cpu = 1; cpu < cores; cpu++) {
 		acpigen_write_processor(cpu, 0, 0);
 		acpigen_pop_len();
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
index f52d230bf2..1ecde23f7a 100644
--- a/src/soc/amd/stoneyridge/acpi/cpu.asl
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -21,14 +21,14 @@ Method (PNOT)
  * Processor Object
  */
 /* These devices are created at runtime */
-External (\_PR.P000, DeviceObj)
-External (\_PR.P001, DeviceObj)
-External (\_PR.P002, DeviceObj)
-External (\_PR.P003, DeviceObj)
-External (\_PR.P004, DeviceObj)
-External (\_PR.P005, DeviceObj)
-External (\_PR.P006, DeviceObj)
-External (\_PR.P007, DeviceObj)
+External (\_SB.P000, DeviceObj)
+External (\_SB.P001, DeviceObj)
+External (\_SB.P002, DeviceObj)
+External (\_SB.P003, DeviceObj)
+External (\_SB.P004, DeviceObj)
+External (\_SB.P005, DeviceObj)
+External (\_SB.P006, DeviceObj)
+External (\_SB.P007, DeviceObj)
 
 /* Return a package containing enabled processor entries */
 Method (PPKG)
@@ -36,21 +36,21 @@ Method (PPKG)
 	If (LGreaterEqual (\PCNT, 4)) {
 		Return (Package ()
 		{
-			\_PR.P000,
-			\_PR.P001,
-			\_PR.P002,
-			\_PR.P003
+			\_SB.P000,
+			\_SB.P001,
+			\_SB.P002,
+			\_SB.P003
 		})
 	} ElseIf (LGreaterEqual (\PCNT, 2)) {
 		Return (Package ()
 		{
-			\_PR.P000,
-			\_PR.P001
+			\_SB.P000,
+			\_SB.P001
 		})
 	} Else {
 		Return (Package ()
 		{
-			\_PR.P000
+			\_SB.P000
 		})
 	}
 }
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index afe7cf0420..3707049130 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -227,6 +227,22 @@ static void northbridge_fill_ssdt_generator(struct device *device)
 	acpigen_pop_len();
 }
 
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+	unsigned int len = ssdt->length - sizeof(acpi_header_t);
+	unsigned int i;
+
+	for (i = sizeof(acpi_header_t); i < len; i++) {
+		/* Search for _PR_ scope and replace it with _SB_ */
+		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+	}
+	/* Recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
+
 static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
@@ -322,6 +338,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
 	if (ssdt != NULL) {
+		patch_ssdt_processor_scope(ssdt);
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *)current;
 		current += ssdt->length;
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 71b2d90a2c..b636c26699 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -488,7 +488,7 @@ static void sb_init_acpi_ports(void)
 	pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
 	pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
 	pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
-	/* CpuControl is in \_PR.CP00, 6 bytes */
+	/* CpuControl is in \_SB.CP00, 6 bytes */
 	pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
 
 	if (CONFIG(HAVE_SMI_HANDLER)) {