diff options
| author | Johnny Li <johnny_li@wistron.corp-partner.google.com> | 2022-09-19 17:31:24 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-09-21 15:33:24 +0000 |
| commit | 93e8f8043417a6adfe909255fc2148563be7cf0d (patch) | |
| tree | 231f9055df58e2d6e39eabe8be7c16bb069ab2c2 | |
| parent | 88a496a9c81ba6447a4c1453a45d09ee79f30309 (diff) | |
mb/google/brya/var/crota: set tcc_offset value to 1 ℃
Set tcc_offset value to 1℃ in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:246913963
TEST=USE="project_crota project_brya" emerge-brya coreboot
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ie2f60bed34fbd6fa3624be60138511a22b199a8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/crota/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 2843748bd3..245d553044 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -79,6 +79,7 @@ chip soc/intel/alderlake register "usb3_ports[0]" = "USB3_PORT_EMPTY" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcc_offset" = "1" # TCC of 99C device domain 0 on device ref dtt on |