diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-11-21 19:50:56 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-11-23 03:37:14 +0000 |
| commit | 8ed53ec8c06c7468a3c4ea1e8fb40012cc375d38 (patch) | |
| tree | e339396debb64d80a242ecca20a7164c6a054e26 | |
| parent | 191bd827344302561c2aa900e5e5ecdd088c5888 (diff) | |
mb/intel/adlrvp: Enable pre-boot display over HDMI-B port
List of changes:
1. Configure CTRLCLK and CTRLDATA for HDMI
2. Enable Ddc and HPD for Port-B
3. Disable dual eDP configuration for Port-A and B
TEST=Able to see depthcharge pre-boot screens over HDMI-B port.
Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/gpio.c | 5 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index ce55fa3914..80edb92003 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -90,7 +90,9 @@ chip soc/intel/alderlake # Enable EDP in PortA register "DdiPortAConfig" = "1" - register "DdiPortBConfig" = "1" + # Enable HDMI in Port B + register "DdiPortBDdc" = "1" + register "DdiPortBHpd" = "1" # TCSS USB3 register "TcssAuxOri" = "0" diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index a44d4ac43d..89e6f5826b 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -287,6 +287,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + + /* A21 : HDMI CRLS CTRLCLK */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22 : HDMI CRLS CTRLDATA */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), }; void variant_configure_gpio_pads(void) |