- Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...

- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

17 files changed, 679 insertions, 389 deletions

diff --git a/src/arch/i386/lib/cpu.c b/src/arch/i386/lib/cpu.c
index 8ace3fbf53..19020fee55 100644
--- a/src/arch/i386/lib/cpu.c
+++ b/src/arch/i386/lib/cpu.c
@@ -68,6 +68,11 @@ static void interrupts_on()
 	low |= APIC_DEFAULT_BASE;
 	wrmsr(APIC_BASE_MSR, low, high);
 
+	/*
+	 * Set Task Priority to 'accept all'.
+	 */
+	apic_write_around(APIC_TASKPRI,
+		apic_read_around(APIC_TASKPRI) & ~APIC_TPRI_MASK);
 
 	/* Put the local apic in virtual wire mode */
 	apic_write_around(APIC_SPIV, 
@@ -91,10 +96,9 @@ static void interrupts_on()
 		| (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING | 
 			APIC_DELIVERY_MODE_NMI)
 		);
-#if 1
+
 	printk_debug(" apic_id: %d ",
 		apic_read(APIC_ID));
-#endif
 
 #else /* APIC */
 #ifdef i686
diff --git a/src/cpu/i386/reset16.inc b/src/cpu/i386/reset16.inc
index 7c911d9ff2..190b75a32d 100644
--- a/src/cpu/i386/reset16.inc
+++ b/src/cpu/i386/reset16.inc
@@ -13,7 +13,7 @@ EXT(reset_vector):
 	 * other assemblers to tell it where the segment registers
 	 * are pointing in memory right now.
 	 */
-	jmp	EXT(_start_offset)
+	jmp	EXT(_start)
 #elif (_ROMBASE < 0x100000)
 	ljmp	$((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset);
 #else
diff --git a/src/cpu/k8/earlymtrr.inc b/src/cpu/k8/earlymtrr.inc
index 903405bdfb..d14afb1a31 100644
--- a/src/cpu/k8/earlymtrr.inc
+++ b/src/cpu/k8/earlymtrr.inc
@@ -46,7 +46,7 @@ set_var_mtrr:
 	wrmsr
 
 #if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
-	/* enable write back cachine so we can do execute in place
+	/* enable write base caching so we can do execute in place
 	 * on the flash rom.
 	 */
 	movl	$0x202, %ecx
diff --git a/src/include/cpu/p6/apic.h b/src/include/cpu/p6/apic.h
index b91cdb2a86..65a14603f5 100644
--- a/src/include/cpu/p6/apic.h
+++ b/src/include/cpu/p6/apic.h
@@ -10,6 +10,8 @@
 
 #define APIC_ID		0x020
 #define APIC_LVR	0x030
+#define	APIC_TASKPRI	0x80
+#define		APIC_TPRI_MASK		0xFF
 #define APIC_ARBID	0x090
 #define	APIC_RRR	0x0C0
 #define APIC_SVR	0x0f0
diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c
index 33dea8e80d..e8e3976ef2 100644
--- a/src/mainboard/amd/solo/auto.c
+++ b/src/mainboard/amd/solo/auto.c
@@ -20,7 +20,9 @@ static int boot_cpu(void)
 	msr = rdmsr(0x1b);
 	bsp = !!(msr.lo & (1 << 8));
 	if (bsp) {
-		print_debug("Bootstrap cpu\r\n");
+		print_debug("Bootstrap processor\r\n");
+	} else {
+		print_debug("Application processor\r\n");
 	}
 
 	return bsp;
@@ -110,14 +112,19 @@ static void dump_spd_registers(void)
 	}
 }
 
-
-
-
 static void main(void)
 {
 	uart_init();
 	console_init();
+#if 0
+	print_debug(" XIP_ROM_BASE: ");
+	print_debug_hex32(XIP_ROM_BASE);
+	print_debug(" XIP_ROM_SIZE: ");
+	print_debug_hex32(XIP_ROM_SIZE);
+	print_debug("\r\n");
+#endif
 	if (boot_cpu() && !cpu_init_detected()) {
+		setup_default_resource_map();
 		setup_coherent_ht_domain();
 		enumerate_ht_chain();
 		print_pci_devices();
@@ -125,17 +132,7 @@ static void main(void)
 		sdram_initialize();
 
 		dump_spd_registers();
-#if 0
-		ram_fill(  0x00100000, 0x00180000);
-		ram_verify(0x00100000, 0x00180000);
-#endif
-#ifdef MEMORY_1024MB
-		ram_fill(  0x00000000, 0x00001000);
-		ram_verify(0x00000000, 0x00001000);
-#endif
-#ifdef MEMROY_512MB
-		ram_fill(  0x00000000, 0x01ffffff);
-		ram_verify(0x00000000, 0x01ffffff);
-#endif
+		/* Check the first 8M */
+		ram_check(0x00100000, 0x00800000);
 	}
 }
diff --git a/src/mainboard/amd/solo/mptable.c b/src/mainboard/amd/solo/mptable.c
index 656b790035..49cd1951e6 100644
--- a/src/mainboard/amd/solo/mptable.c
+++ b/src/mainboard/amd/solo/mptable.c
@@ -7,8 +7,8 @@
 void *smp_write_config_table(void *v, unsigned long * processor_map)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
-	static const char productid[12] = "P4DPR       ";
+	static const char oem[8] = "AMD     ";
+	static const char productid[12] = "SOLO7       ";
 	struct mp_config_table *mc;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 81f044cc13..68d8b39e36 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -1,3 +1,11 @@
+#define COHERENT_AMD_SOLO    1 /* AMD Solo motherboard */
+#define COHERENT_ARIMA_HDAMA 2 /* Arima HDAMA motherboard */
+
+#ifndef COHERENT_CONFIG
+#define COHERENT_CONFIG COHERENT_AMD_SOLO
+#endif
+
+
 static void setup_coherent_ht_domain(void)
 {
 	static const unsigned int register_values[] = {
@@ -296,278 +304,6 @@ static void setup_coherent_ht_domain(void)
 	 * F0:0xB8 i = 1,
 	 * F0:0xD8 i = 2,
 	 */
-	/* Careful set limit registers before base registers which contain the enables */
-	/* DRAM Limit i Registers
-	 * F1:0x44 i = 0
-	 * F1:0x4C i = 1
-	 * F1:0x54 i = 2
-	 * F1:0x5C i = 3
-	 * F1:0x64 i = 4
-	 * F1:0x6C i = 5
-	 * F1:0x74 i = 6
-	 * F1:0x7C i = 7
-	 * [ 2: 0] Destination Node ID
-	 *         000 = Node 0
-	 *         001 = Node 1
-	 *         010 = Node 2
-	 *         011 = Node 3
-	 *         100 = Node 4
-	 *         101 = Node 5
-	 *         110 = Node 6
-	 *         111 = Node 7
-	 * [ 7: 3] Reserved
-	 * [10: 8] Interleave select
-	 *         specifies the values of A[14:12] to use with interleave enable.
-	 * [15:11] Reserved
-	 * [31:16] DRAM Limit Address i Bits 39-24
-	 *         This field defines the upper address bits of a 40 bit  address
-	 *         that define the end of the DRAM region.
-	 */
-#if MEMORY_1024MB
-	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
-#endif
-#if MEMORY_512MB
-	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
-#endif
-	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-	/* DRAM Base i Registers
-	 * F1:0x40 i = 0
-	 * F1:0x48 i = 1
-	 * F1:0x50 i = 2
-	 * F1:0x58 i = 3
-	 * F1:0x60 i = 4
-	 * F1:0x68 i = 5
-	 * F1:0x70 i = 6
-	 * F1:0x78 i = 7
-	 * [ 0: 0] Read Enable
-	 *         0 = Reads Disabled
-	 *         1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *         0 = Writes Disabled
-	 *         1 = Writes Enabled
-	 * [ 7: 2] Reserved
-	 * [10: 8] Interleave Enable
-	 *         000 = No interleave
-	 *         001 = Interleave on A[12] (2 nodes)
-	 *         010 = reserved
-	 *         011 = Interleave on A[12] and A[14] (4 nodes)
-	 *         100 = reserved
-	 *         101 = reserved
-	 *         110 = reserved
-	 *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-	 * [15:11] Reserved
-	 * [13:16] DRAM Base Address i Bits 39-24
-	 *         This field defines the upper address bits of a 40-bit address
-	 *         that define the start of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
-#if MEMORY_1024MB
-	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
-	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
-	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
-	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
-	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
-	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
-	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
-#endif
-#if MEMORY_512MB
-	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
-	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
-	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
-	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
-	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
-	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
-	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
-#endif
-
-	/* Memory-Mapped I/O Limit i Registers
-	 * F1:0x84 i = 0
-	 * F1:0x8C i = 1
-	 * F1:0x94 i = 2
-	 * F1:0x9C i = 3
-	 * F1:0xA4 i = 4
-	 * F1:0xAC i = 5
-	 * F1:0xB4 i = 6
-	 * F1:0xBC i = 7
-	 * [ 2: 0] Destination Node ID
-	 *         000 = Node 0
-	 *         001 = Node 1
-	 *         010 = Node 2
-	 *         011 = Node 3
-	 *         100 = Node 4
-	 *         101 = Node 5
-	 *         110 = Node 6
-	 *         111 = Node 7
-	 * [ 3: 3] Reserved
-	 * [ 5: 4] Destination Link ID
-	 *         00 = Link 0
-	 *         01 = Link 1
-	 *         10 = Link 2
-	 *         11 = Reserved
-	 * [ 6: 6] Reserved
-	 * [ 7: 7] Non-Posted
-	 *         0 = CPU writes may be posted
-	 *         1 = CPU writes must be non-posted
-	 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-	 *         This field defines the upp adddress bits of a 40-bit address that
-	 *         defines the end of a memory-mapped I/O region n
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
-	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
-	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
-	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
-	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
-
-	/* Memory-Mapped I/O Base i Registers
-	 * F1:0x80 i = 0
-	 * F1:0x88 i = 1
-	 * F1:0x90 i = 2
-	 * F1:0x98 i = 3
-	 * F1:0xA0 i = 4
-	 * F1:0xA8 i = 5
-	 * F1:0xB0 i = 6
-	 * F1:0xB8 i = 7
-	 * [ 0: 0] Read Enable
-	 *         0 = Reads disabled
-	 *         1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *         0 = Writes disabled
-	 *         1 = Writes Enabled
-	 * [ 2: 2] Cpu Disable
-	 *         0 = Cpu can use this I/O range
-	 *         1 = Cpu requests do not use this I/O range
-	 * [ 3: 3] Lock
-	 *         0 = base/limit registers i are read/write
-	 *         1 = base/limit registers i are read-only
-	 * [ 7: 4] Reserved
-	 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-	 *         This field defines the upper address bits of a 40bit address 
-	 *         that defines the start of memory-mapped I/O region i
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
-	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
-	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
-	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
-#if MEMORY_1024MB
-	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
-#endif
-#if MEMORY_512MB
-	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
-#endif
-
-	/* PCI I/O Limit i Registers
-	 * F1:0xC4 i = 0
-	 * F1:0xCC i = 1
-	 * F1:0xD4 i = 2
-	 * F1:0xDC i = 3
-	 * [ 2: 0] Destination Node ID
-	 *         000 = Node 0
-	 *         001 = Node 1
-	 *         010 = Node 2
-	 *         011 = Node 3
-	 *         100 = Node 4
-	 *         101 = Node 5
-	 *         110 = Node 6
-	 *         111 = Node 7
-	 * [ 3: 3] Reserved
-	 * [ 5: 4] Destination Link ID
-	 *         00 = Link 0
-	 *         01 = Link 1
-	 *         10 = Link 2
-	 *         11 = reserved
-	 * [11: 6] Reserved
-	 * [24:12] PCI I/O Limit Address i
-	 *         This field defines the end of PCI I/O region n
-	 * [31:25] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
-	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
-	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
-	/* PCI I/O Base i Registers
-	 * F1:0xC0 i = 0
-	 * F1:0xC8 i = 1
-	 * F1:0xD0 i = 2
-	 * F1:0xD8 i = 3
-	 * [ 0: 0] Read Enable
-	 *         0 = Reads Disabled
-	 *         1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *         0 = Writes Disabled
-	 *         1 = Writes Enabled
-	 * [ 3: 2] Reserved
-	 * [ 4: 4] VGA Enable
-	 *         0 = VGA matches Disabled
-	 *         1 = matches all address < 64K and where A[9:0] is in the 
-	 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
-	 * [ 5: 5] ISA Enable
-	 *         0 = ISA matches Disabled
-	 *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
-	 *             from matching agains this base/limit pair
-	 * [11: 6] Reserved
-	 * [24:12] PCI I/O Base i
-	 *         This field defines the start of PCI I/O region n 
-	 * [31:25] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
-	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
-	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
-	/* Config Base and Limit i Registers
-	 * F1:0xE0 i = 0
-	 * F1:0xE4 i = 1
-	 * F1:0xE8 i = 2
-	 * F1:0xEC i = 3
-	 * [ 0: 0] Read Enable
-	 *         0 = Reads Disabled
-	 *         1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *         0 = Writes Disabled
-	 *         1 = Writes Enabled
-	 * [ 2: 2] Device Number Compare Enable
-	 *         0 = The ranges are based on bus number
-	 *         1 = The ranges are ranges of devices on bus 0
-	 * [ 3: 3] Reserved
-	 * [ 6: 4] Destination Node
-	 *         000 = Node 0
-	 *         001 = Node 1
-	 *         010 = Node 2
-	 *         011 = Node 3
-	 *         100 = Node 4
-	 *         101 = Node 5
-	 *         110 = Node 6
-	 *         111 = Node 7
-	 * [ 7: 7] Reserved
-	 * [ 9: 8] Destination Link
-	 *         00 = Link 0
-	 *         01 = Link 1
-	 *         10 = Link 2
-	 *         11 - Reserved
-	 * [15:10] Reserved
-	 * [23:16] Bus Number Base i
-	 *         This field defines the lowest bus number in configuration region i
-	 * [31:24] Bus Number Limit i
-	 *         This field defines the highest bus number in configuration regin i
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
-	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
 	};
 	int i;
 	int max;
@@ -598,4 +334,3 @@ static void setup_coherent_ht_domain(void)
 	}
 	print_debug("done.\r\n");
 }
-
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 1f43e48671..6c757c993e 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1,9 +1,305 @@
-#define MEMORY_512MB  0  /* SuSE Solo configuration */
-#define MEMORY_1024MB 1  /* LNXI Solo configuration */
+#define MEMORY_SUSE_SOLO  1 /* SuSE Solo configuration */
+#define MEMORY_LNXI_SOLO  2 /* LNXI Solo configuration */
+#define MEMORY_LNXI_HDAMA 3 /* LNXI HDAMA configuration */
+
+
+#ifndef MEMORY_CONFIG
+#define MEMORY_CONFIG MEMORY_SUSE_SOLO
+#endif
+
+static void setup_resource_map(const unsigned int *register_values, int max)
+{
+	int i;
+	print_debug("setting up resource map....\r\n");
+	for(i = 0; i < max; i += 3) {
+		device_t dev;
+		unsigned where;
+		unsigned long reg;
+#if 0
+		print_debug_hex32(register_values[i]);
+		print_debug(" <-");
+		print_debug_hex32(register_values[i+2]);
+		print_debug("\r\n");
+#endif
+		dev = register_values[i] & ~0xff;
+		where = register_values[i] & 0xff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		pci_write_config32(dev, where, reg);
+#if 0
+		reg = pci_read_config32(register_values[i]);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2] & ~register_values[i+1];
+		pci_write_config32(register_values[i], reg);
+#endif
+	}
+	print_debug("done.\r\n");
+}
+
+static void setup_default_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+	/* Careful set limit registers before base registers which contain the enables */
+	/* DRAM Limit i Registers
+	 * F1:0x44 i = 0
+	 * F1:0x4C i = 1
+	 * F1:0x54 i = 2
+	 * F1:0x5C i = 3
+	 * F1:0x64 i = 4
+	 * F1:0x6C i = 5
+	 * F1:0x74 i = 6
+	 * F1:0x7C i = 7
+	 * [ 2: 0] Destination Node ID
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 7: 3] Reserved
+	 * [10: 8] Interleave select
+	 *         specifies the values of A[14:12] to use with interleave enable.
+	 * [15:11] Reserved
+	 * [31:16] DRAM Limit Address i Bits 39-24
+	 *         This field defines the upper address bits of a 40 bit  address
+	 *         that define the end of the DRAM region.
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+	/* DRAM Base i Registers
+	 * F1:0x40 i = 0
+	 * F1:0x48 i = 1
+	 * F1:0x50 i = 2
+	 * F1:0x58 i = 3
+	 * F1:0x60 i = 4
+	 * F1:0x68 i = 5
+	 * F1:0x70 i = 6
+	 * F1:0x78 i = 7
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads Disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes Disabled
+	 *         1 = Writes Enabled
+	 * [ 7: 2] Reserved
+	 * [10: 8] Interleave Enable
+	 *         000 = No interleave
+	 *         001 = Interleave on A[12] (2 nodes)
+	 *         010 = reserved
+	 *         011 = Interleave on A[12] and A[14] (4 nodes)
+	 *         100 = reserved
+	 *         101 = reserved
+	 *         110 = reserved
+	 *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+	 * [15:11] Reserved
+	 * [13:16] DRAM Base Address i Bits 39-24
+	 *         This field defines the upper address bits of a 40-bit address
+	 *         that define the start of the DRAM region.
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+	/* Memory-Mapped I/O Limit i Registers
+	 * F1:0x84 i = 0
+	 * F1:0x8C i = 1
+	 * F1:0x94 i = 2
+	 * F1:0x9C i = 3
+	 * F1:0xA4 i = 4
+	 * F1:0xAC i = 5
+	 * F1:0xB4 i = 6
+	 * F1:0xBC i = 7
+	 * [ 2: 0] Destination Node ID
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 3: 3] Reserved
+	 * [ 5: 4] Destination Link ID
+	 *         00 = Link 0
+	 *         01 = Link 1
+	 *         10 = Link 2
+	 *         11 = Reserved
+	 * [ 6: 6] Reserved
+	 * [ 7: 7] Non-Posted
+	 *         0 = CPU writes may be posted
+	 *         1 = CPU writes must be non-posted
+	 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+	 *         This field defines the upp adddress bits of a 40-bit address that
+	 *         defines the end of a memory-mapped I/O region n
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00000000,
+
+	/* Memory-Mapped I/O Base i Registers
+	 * F1:0x80 i = 0
+	 * F1:0x88 i = 1
+	 * F1:0x90 i = 2
+	 * F1:0x98 i = 3
+	 * F1:0xA0 i = 4
+	 * F1:0xA8 i = 5
+	 * F1:0xB0 i = 6
+	 * F1:0xB8 i = 7
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes disabled
+	 *         1 = Writes Enabled
+	 * [ 2: 2] Cpu Disable
+	 *         0 = Cpu can use this I/O range
+	 *         1 = Cpu requests do not use this I/O range
+	 * [ 3: 3] Lock
+	 *         0 = base/limit registers i are read/write
+	 *         1 = base/limit registers i are read-only
+	 * [ 7: 4] Reserved
+	 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+	 *         This field defines the upper address bits of a 40bit address 
+	 *         that defines the start of memory-mapped I/O region i
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00000000,
+
+	/* PCI I/O Limit i Registers
+	 * F1:0xC4 i = 0
+	 * F1:0xCC i = 1
+	 * F1:0xD4 i = 2
+	 * F1:0xDC i = 3
+	 * [ 2: 0] Destination Node ID
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 3: 3] Reserved
+	 * [ 5: 4] Destination Link ID
+	 *         00 = Link 0
+	 *         01 = Link 1
+	 *         10 = Link 2
+	 *         11 = reserved
+	 * [11: 6] Reserved
+	 * [24:12] PCI I/O Limit Address i
+	 *         This field defines the end of PCI I/O region n
+	 * [31:25] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+	/* PCI I/O Base i Registers
+	 * F1:0xC0 i = 0
+	 * F1:0xC8 i = 1
+	 * F1:0xD0 i = 2
+	 * F1:0xD8 i = 3
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads Disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes Disabled
+	 *         1 = Writes Enabled
+	 * [ 3: 2] Reserved
+	 * [ 4: 4] VGA Enable
+	 *         0 = VGA matches Disabled
+	 *         1 = matches all address < 64K and where A[9:0] is in the 
+	 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+	 * [ 5: 5] ISA Enable
+	 *         0 = ISA matches Disabled
+	 *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+	 *             from matching agains this base/limit pair
+	 * [11: 6] Reserved
+	 * [24:12] PCI I/O Base i
+	 *         This field defines the start of PCI I/O region n 
+	 * [31:25] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
+	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+	/* Config Base and Limit i Registers
+	 * F1:0xE0 i = 0
+	 * F1:0xE4 i = 1
+	 * F1:0xE8 i = 2
+	 * F1:0xEC i = 3
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads Disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes Disabled
+	 *         1 = Writes Enabled
+	 * [ 2: 2] Device Number Compare Enable
+	 *         0 = The ranges are based on bus number
+	 *         1 = The ranges are ranges of devices on bus 0
+	 * [ 3: 3] Reserved
+	 * [ 6: 4] Destination Node
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 7: 7] Reserved
+	 * [ 9: 8] Destination Link
+	 *         00 = Link 0
+	 *         01 = Link 1
+	 *         10 = Link 2
+	 *         11 - Reserved
+	 * [15:10] Reserved
+	 * [23:16] Bus Number Base i
+	 *         This field defines the lowest bus number in configuration region i
+	 * [31:24] Bus Number Limit i
+	 *         This field defines the highest bus number in configuration regin i
+	 */
+	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
+	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+	int max;
+	max = sizeof(register_values)/sizeof(register_values[0]);
+	setup_resource_map(register_values, max);
+}
 
 static void sdram_set_registers(void)
 {
 	static const unsigned int register_values[] = {
+
 	/* Careful set limit registers before base registers which contain the enables */
 	/* DRAM Limit i Registers
 	 * F1:0x44 i = 0
@@ -31,13 +327,18 @@ static void sdram_set_registers(void)
 	 *         This field defines the upper address bits of a 40 bit  address
 	 *         that define the end of the DRAM region.
 	 */
-#if MEMORY_1024MB
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
+	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
-#endif
 	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
+	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x007f0001,
+#endif
 	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
 	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
 	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
@@ -75,7 +376,7 @@ static void sdram_set_registers(void)
 	 *         that define the start of the DRAM region.
 	 */
 	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
-#if MEMORY_1024MB
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
 	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
 	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
@@ -84,7 +385,7 @@ static void sdram_set_registers(void)
 	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
 	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
 	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
 	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
@@ -93,6 +394,16 @@ static void sdram_set_registers(void)
 	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
 	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
 #endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400003,
+	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00800000,
+	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00800000,
+	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00800000,
+	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00800000,
+	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00800000,
+	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00800000,
+	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00800000,
+#endif
 
 	/* Memory-Mapped I/O Limit i Registers
 	 * F1:0x84 i = 0
@@ -126,6 +437,7 @@ static void sdram_set_registers(void)
 	 *         This field defines the upp adddress bits of a 40-bit address that
 	 *         defines the end of a memory-mapped I/O region n
 	 */
+#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
 	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
 	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
 	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
@@ -134,6 +446,17 @@ static void sdram_set_registers(void)
 	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
 	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00fe2f00,
+	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00fec000,
+	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x0000b000,
+	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00000000,
+#endif
 
 	/* Memory-Mapped I/O Base i Registers
 	 * F1:0x80 i = 0
@@ -161,6 +484,7 @@ static void sdram_set_registers(void)
 	 *         This field defines the upper address bits of a 40bit address 
 	 *         that defines the start of memory-mapped I/O region i
 	 */
+#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
 	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
 	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
 	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
@@ -168,12 +492,23 @@ static void sdram_set_registers(void)
 	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
-#if MEMORY_1024MB
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
 #endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00fc0003,
+	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00fec00e,
+	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03,
+	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00000000,
+#endif
 
 	/* PCI I/O Limit i Registers
 	 * F1:0xC4 i = 0
@@ -200,10 +535,18 @@ static void sdram_set_registers(void)
 	 *         This field defines the end of PCI I/O region n
 	 * [31:25] Reserved
 	 */
+#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
 	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
 	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
 	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+#endif
 
 	/* PCI I/O Base i Registers
 	 * F1:0xC0 i = 0
@@ -230,10 +573,18 @@ static void sdram_set_registers(void)
 	 *         This field defines the start of PCI I/O region n 
 	 * [31:25] Reserved
 	 */
+#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
 	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
 	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
 	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+#endif
 
 	/* Config Base and Limit i Registers
 	 * F1:0xE0 i = 0
@@ -271,10 +622,18 @@ static void sdram_set_registers(void)
 	 * [31:24] Bus Number Limit i
 	 *         This field defines the highest bus number in configuration regin i
 	 */
+#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
 	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
 	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
+	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+#endif
 
 	/* DRAM CS Base Address i Registers
 	 * F2:0x40 i = 0
@@ -298,16 +657,21 @@ static void sdram_set_registers(void)
 	 *         bits decode 32-MByte blocks of memory.
 	 */
 	PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000001,
-#if MEMORY_1024MB
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x01000001,
 	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x02000001,
 	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x03000001,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00800001,
 	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x01000001,
 	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x01800001,
 #endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00001001,
+	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
+#endif
 	PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
 	PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
 	PCI_ADDR(0, 0x18, 2, 0x58), 0x001f01fe, 0x00000000,
@@ -331,18 +695,24 @@ static void sdram_set_registers(void)
 	 * [31:30] Reserved
 	 * 
 	 */
-#if MEMORY_1024MB
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00e0fe00,
 	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00e0fe00,
 	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00e0fe00,
 	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00e0fe00,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x0060fe00,
 	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x0060fe00,
 	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x0060fe00,
 	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x0060fe00,
 #endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x03e0ee00,
+	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x03e0ee00,
+	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
+#endif
 	PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
 	PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
 	PCI_ADDR(0, 0x18, 2, 0x78), 0xC01f01ff, 0x00000000,
@@ -367,12 +737,15 @@ static void sdram_set_registers(void)
 	 * [11:11] Reserved
 	 * [31:15]
 	 */
-#if MEMORY_1024MB
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000033,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000022,
 #endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000003,
+#endif
 	/* DRAM Timing Low Register
 	 * F2:0x88
 	 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
@@ -437,7 +810,12 @@ static void sdram_set_registers(void)
 	 *         1 = 3 bus clocks
 	 * [31:29] Reserved
 	 */
+#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
 	PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x03623125,
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x13723335,
+#endif
 	/* DRAM Timing High Register
 	 * F2:0x8C
 	 * [ 0: 0] Twtr (Write to Read Delay)
@@ -467,13 +845,15 @@ static void sdram_set_registers(void)
 	 *         001 = 2 Mem clocks after CAS# (Registered Dimms)
 	 * [31:23] Reserved
 	 */
-#if MEMORY_1024MB
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, 0x00000930,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, 0x00000130,
 #endif
-
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, 0x00100a20,
+#endif
 	/* DRAM Config Low Register
 	 * F2:0x90
 	 * [ 0: 0] DLL Disable
@@ -544,6 +924,7 @@ static void sdram_set_registers(void)
 	 *         111 = Oldest entry in DCQ can be bypassed 7 times
 	 * [31:28] Reserved
 	 */
+#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
 	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
 	(4 << 25)|(0 << 24)| 
 	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
@@ -551,6 +932,16 @@ static void sdram_set_registers(void)
 	(2 << 14)|(0 << 13)|(0 << 12)| 
 	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
 	(0 << 3) |(0 << 1) |(0 << 0),
+#endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
+	(4 << 25)|(0 << 24)|
+	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
+	(0 << 19)|(0 << 18)|(0 << 17)|(1 << 16)|
+	(2 << 14)|(0 << 13)|(0 << 12)|
+	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
+	(0 << 3) |(0 << 1) |(0 << 0),
+#endif
 	/* DRAM Config High Register
 	 * F2:0x94
 	 * [ 0: 3] Maximum Asynchronous Latency
@@ -615,12 +1006,15 @@ static void sdram_set_registers(void)
 	 *         1 = Enabled
 	 * [31:30] Reserved
 	 */
-#if MEMORY_1024MB
+#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0, 0x0e2b0a05,
 #endif
-#if MEMORY_512MB
+#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
 	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0, 0x0e2b0a06,
 #endif
+#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
+	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0, 0x065b0b08,
+#endif
 	/* DRAM Delay Line Register
 	 * F2:0x98
 	 * Adjust the skew of the input DQS strobe relative to DATA
diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c
index 1d268f0482..96f8f5d0a4 100644
--- a/src/pc80/mc146818rtc_early.c
+++ b/src/pc80/mc146818rtc_early.c
@@ -1,6 +1,13 @@
 #include <pc80/mc146818rtc.h>
 #include <part/fallback_boot.h>
 
+#ifndef MAX_REBOOT_CNT
+#error "MAX_REBOOT_CNT not defined"
+#endif
+#if  MAX_REBOOT_CNT > 15
+#error "MAX_REBOOT_CNT too high"
+#endif
+
 static unsigned char cmos_read(unsigned char addr)
 {
 	outb(addr, RTC_BASE_PORT + 0);
diff --git a/src/ram/ramtest.c b/src/ram/ramtest.c
index 55c22e7084..068d3bd705 100644
--- a/src/ram/ramtest.c
+++ b/src/ram/ramtest.c
@@ -1,8 +1,24 @@
+#if defined(i786)
+#define HAVE_MOVNTI 1
+#endif
+#if defined(k8)
+#define HAVE_MOVNTI 1
+#endif
+
 static void write_phys(unsigned long addr, unsigned long value)
 {
+#if HAVE_MOVNTI
+	asm volatile(
+		"movnti %1, (%0)"
+		: /* outputs */
+		: "r" (addr), "r" (value) /* inputs */
+		: /* clobbers */
+		);
+#else
 	volatile unsigned long *ptr;
 	ptr = (void *)addr;
 	*ptr = value;
+#endif
 }
 
 static unsigned long read_phys(unsigned long addr)
@@ -12,7 +28,7 @@ static unsigned long read_phys(unsigned long addr)
 	return *ptr;
 }
 
-void ram_fill(unsigned long start, unsigned long stop)
+static void ram_fill(unsigned long start, unsigned long stop)
 {
 	unsigned long addr;
 	/* 
@@ -25,7 +41,7 @@ void ram_fill(unsigned long start, unsigned long stop)
 	print_debug("\r\n");
 	for(addr = start; addr < stop ; addr += 4) {
 		/* Display address being filled */
-		if ((addr & 0xffff) == 0) {
+		if (!(addr & 0xffff)) {
 			print_debug_hex32(addr);
 			print_debug("\r");
 		}
@@ -36,7 +52,7 @@ void ram_fill(unsigned long start, unsigned long stop)
 	print_debug("\r\nDRAM filled\r\n");
 }
 
-void ram_verify(unsigned long start, unsigned long stop)
+static void ram_verify(unsigned long start, unsigned long stop)
 {
 	unsigned long addr;
 	/* 
@@ -50,7 +66,7 @@ void ram_verify(unsigned long start, unsigned long stop)
 	for(addr = start; addr < stop ; addr += 4) {
 		unsigned long value;
 		/* Display address being tested */
-		if ((addr & 0xffff) == 0) {
+		if (!(addr & 0xffff)) {
 			print_debug_hex32(addr);
 			print_debug("\r");
 		}
@@ -69,7 +85,7 @@ void ram_verify(unsigned long start, unsigned long stop)
 }
 
 
-void ramcheck(unsigned long start, unsigned long stop)
+void ram_check(unsigned long start, unsigned long stop)
 {
 	int result;
 	/*
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index f098bfa2b4..643b84cad9 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -1,5 +1,5 @@
 /*
- * (C) 2003 Linux Networx 
+ * (C) 2003 Linux Networx, SuSE Linux AG
  */
 #include <console/console.h>
 #include <device/device.h>
@@ -28,38 +28,33 @@ static struct ioapicreg ioapicregvalues[] = {
 #define NMI		(4 << 8)
 #define SMI		(2 << 8)
 #define INT		(1 << 8)
+	/* IO-APIC virtual wire mode configuration */
 	/* mask, trigger, polarity, destination, delivery, vector */
-	{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
-	{0x01, DISABLED, NONE},
-	{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0,  0},
-	{0x03, DISABLED, NONE},
-	{0x04, DISABLED, NONE},
-	{0x05, DISABLED, NONE},
-	{0x06, DISABLED, NONE},
-	{0x07, DISABLED, NONE},
-	{0x08, DISABLED, NONE},
-	{0x09, DISABLED, NONE},
-	{0x0a, DISABLED, NONE},
-	{0x0b, DISABLED, NONE},
-	{0x0c, DISABLED, NONE},
-	{0x0d, DISABLED, NONE},
-	{0x0e, DISABLED, NONE},
-	{0x0f, DISABLED, NONE},
-	{0x10, DISABLED, NONE},
-	{0x11, DISABLED, NONE},
-	{0x12, DISABLED, NONE},
-	{0x13, DISABLED, NONE},
-	{0x14, DISABLED, NONE},
-	{0x14, DISABLED, NONE},
-	{0x15, DISABLED, NONE},
-	{0x16, DISABLED, NONE},
-	{0x17, DISABLED, NONE},
-	{0x18, DISABLED, NONE},
-	{0x19, DISABLED, NONE},
-	{0x20, DISABLED, NONE},
-	{0x21, DISABLED, NONE},
-	{0x22, DISABLED, NONE},
-	{0x23, DISABLED, NONE},
+	{   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
+	{   1, DISABLED, NONE},
+	{   2, DISABLED, NONE},
+	{   3, DISABLED, NONE},
+	{   4, DISABLED, NONE},
+	{   5, DISABLED, NONE},
+	{   6, DISABLED, NONE},
+	{   7, DISABLED, NONE},
+	{   8, DISABLED, NONE},
+	{   9, DISABLED, NONE},
+	{  10, DISABLED, NONE},
+	{  11, DISABLED, NONE},
+	{  12, DISABLED, NONE},
+	{  13, DISABLED, NONE},
+	{  14, DISABLED, NONE},
+	{  15, DISABLED, NONE},
+	{  16, DISABLED, NONE},
+	{  17, DISABLED, NONE},
+	{  18, DISABLED, NONE},
+	{  19, DISABLED, NONE},
+	{  20, DISABLED, NONE},
+	{  21, DISABLED, NONE},
+	{  22, DISABLED, NONE},
+	{  23, DISABLED, NONE},
+	/* Be careful and don't write past the end... */
 };
 
 static void setup_ioapic(void)
@@ -71,6 +66,7 @@ static void setup_ioapic(void)
 	struct ioapicreg *a = ioapicregvalues;
 
 	l = (unsigned long *) ioapic_base;
+
 	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
@@ -95,13 +91,11 @@ static void lpc_init(struct device *dev)
 
 	printk_debug("lpc_init\n");
 
-#if 0
 	/* IO APIC initialization */
 	byte = pci_read_config8(dev, 0x4B);
 	byte |= 1;
 	pci_write_config8(dev, 0x4B, byte);
 	setup_ioapic();
-#endif
 
 	/* posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
diff --git a/util/nrv2b/nrv2b.c b/util/nrv2b/nrv2b.c
index fca16b4e96..b9e1c10648 100644
--- a/util/nrv2b/nrv2b.c
+++ b/util/nrv2b/nrv2b.c
@@ -43,6 +43,7 @@
 #include <netinet/in.h>
 #endif
 
+
 #ifndef VERBOSE
 #define Fprintf(x)
 #define wterr     0
diff --git a/util/romcc/Makefile b/util/romcc/Makefile
index 9909b87d5a..be2d031055 100644
--- a/util/romcc/Makefile
+++ b/util/romcc/Makefile
@@ -50,6 +50,7 @@ TESTS=\
 	simple_test29.c \
 	simple_test30.c \
 	simple_test31.c \
+	simple_test32.c \
 	raminit_test.c \
 	raminit_test2.c \
 	raminit_test3.c \
diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c
index d0e13e2d2c..7aea1b40b8 100644
--- a/util/romcc/romcc.c
+++ b/util/romcc/romcc.c
@@ -9,7 +9,6 @@
 #include <unistd.h>
 #include <stdio.h>
 #include <string.h>
-#include <ctype.h>
 #include <limits.h>
 
 #define DEBUG_ERROR_MESSAGES 0
@@ -18,6 +17,7 @@
 #define DEBUG_CONSISTENCY 1
 
 #warning "FIXME boundary cases with small types in larger registers"
+#warning "FIXME give clear error messages about unused variables"
 
 /*  Control flow graph of a loop without goto.
  * 
@@ -864,6 +864,10 @@ struct type {
 #define REG_VIRT3          (MAX_REGISTERS + 3)
 #define REG_VIRT4          (MAX_REGISTERS + 4)
 #define REG_VIRT5          (MAX_REGISTERS + 5)
+#define REG_VIRT6          (MAX_REGISTERS + 5)
+#define REG_VIRT7          (MAX_REGISTERS + 5)
+#define REG_VIRT8          (MAX_REGISTERS + 5)
+#define REG_VIRT9          (MAX_REGISTERS + 5)
 
 /* Provision for 8 register classes */
 #if 1
@@ -2156,6 +2160,14 @@ static int digitp(int c)
 	}
 	return ret;
 }
+static int digval(int c)
+{
+	int val = -1;
+	if ((c >= '0') && (c <= '9')) {
+		val = c - '0';
+	}
+	return val;
+}
 
 static int hexdigitp(int c)
 {
@@ -3262,7 +3274,12 @@ static void preprocess(struct compile_state *state, int index)
 		}
 		/* Error if there are any characters after the include */
 		for(ptr = file->pos; *ptr != '\n'; ptr++) {
-			if (!isspace(*ptr)) {
+			switch(*ptr) {
+			case ' ':
+			case '\t':
+			case '\v':
+				break;
+			default:
 				error(state, 0, "garbage after include directive");
 			}
 		}
@@ -4916,9 +4933,13 @@ static struct triple *flatten(
 			}
 			break;
 		}
+		case OP_PIECE:
+			MISC(ptr, 0) = flatten(state, first, MISC(ptr, 0));
+			use_triple(MISC(ptr, 0), ptr);
+			use_triple(ptr, MISC(ptr, 0));
+			break;
 		case OP_ADDRCONST:
 		case OP_SDECL:
-		case OP_PIECE:
 			MISC(ptr, 0) = flatten(state, first, MISC(ptr, 0));
 			use_triple(MISC(ptr, 0), ptr);
 			break;
@@ -7639,11 +7660,17 @@ static void asm_statement(struct compile_state *state, struct triple *first)
 		while(more) {
 			struct triple *var;
 			struct triple *constraint;
+			char *str;
 			more = 0;
 			if (out > MAX_LHS) {
 				error(state, 0, "Maximum output count exceeded.");
 			}
 			constraint = string_constant(state);
+			str = constraint->u.blob;
+			if (str[0] != '=') {
+				error(state, 0, "Output constraint does not start with =");
+			}
+			constraint->u.blob = str + 1;
 			eat(state, TOK_LPAREN);
 			var = conditional_expr(state);
 			eat(state, TOK_RPAREN);
@@ -7666,11 +7693,20 @@ static void asm_statement(struct compile_state *state, struct triple *first)
 		while(more) {
 			struct triple *val;
 			struct triple *constraint;
+			char *str;
 			more = 0;
 			if (in > MAX_RHS) {
 				error(state, 0, "Maximum input count exceeded.");
 			}
 			constraint = string_constant(state);
+			str = constraint->u.blob;
+			if (digitp(str[0] && str[1] == '\0')) {
+				int val;
+				val = digval(str[0]);
+				if ((val < 0) || (val >= out)) {
+					error(state, 0, "Invalid input constraint %d", val);
+				}
+			}
 			eat(state, TOK_LPAREN);
 			val = conditional_expr(state);
 			eat(state, TOK_RPAREN);
@@ -7717,41 +7753,68 @@ static void asm_statement(struct compile_state *state, struct triple *first)
 
 	def = new_triple(state, OP_ASM, &void_type, clobbers + out, in);
 	def->u.ainfo = info;
+
+	/* Find the register constraints */
+	for(i = 0; i < out; i++) {
+		struct triple *constraint;
+		constraint = out_param[i].constraint;
+		info->tmpl.lhs[i] = arch_reg_constraint(state, 
+			out_param[i].expr->type, constraint->u.blob);
+		free_triple(state, constraint);
+	}
+	for(; i - out < clobbers; i++) {
+		struct triple *constraint;
+		constraint = clob_param[i - out].constraint;
+		info->tmpl.lhs[i] = arch_reg_clobber(state, constraint->u.blob);
+		free_triple(state, constraint);
+	}
 	for(i = 0; i < in; i++) {
 		struct triple *constraint;
+		const char *str;
 		constraint = in_param[i].constraint;
-		info->tmpl.rhs[i] = arch_reg_constraint(state, 
-			in_param[i].expr->type, constraint->u.blob);
+		str = constraint->u.blob;
+		if (digitp(str[0]) && str[1] == '\0') {
+			struct reg_info cinfo;
+			int val;
+			val = digval(str[0]);
+			cinfo.reg = info->tmpl.lhs[val].reg;
+			cinfo.regcm = arch_type_to_regcm(state, in_param[i].expr->type);
+			cinfo.regcm &= info->tmpl.lhs[val].regcm;
+			if (cinfo.reg == REG_UNSET) {
+				cinfo.reg = REG_VIRT0 + val;
+			}
+			if (cinfo.regcm == 0) {
+				error(state, 0, "No registers for %d", val);
+			}
+			info->tmpl.lhs[val] = cinfo;
+			info->tmpl.rhs[i]   = cinfo;
+				
+		} else {
+			info->tmpl.rhs[i] = arch_reg_constraint(state, 
+				in_param[i].expr->type, str);
+		}
+		free_triple(state, constraint);
+	}
 
+	/* Now build the helper expressions */
+	for(i = 0; i < in; i++) {
 		RHS(def, i) = read_expr(state,in_param[i].expr);
-		free_triple(state, constraint);
 	}
 	flatten(state, first, def);
 	for(i = 0; i < out; i++) {
 		struct triple *piece;
-		struct triple *constraint;
-		constraint = out_param[i].constraint;
-		info->tmpl.lhs[i] = arch_reg_constraint(state,
-			out_param[i].expr->type, constraint->u.blob);
-
 		piece = triple(state, OP_PIECE, out_param[i].expr->type, def, 0);
 		piece->u.cval = i;
 		LHS(def, i) = piece;
 		flatten(state, first,
 			write_expr(state, out_param[i].expr, piece));
-		free_triple(state, constraint);
 	}
 	for(; i - out < clobbers; i++) {
 		struct triple *piece;
-		struct triple *constraint;
-		constraint = clob_param[i - out].constraint;
-		info->tmpl.lhs[i] = arch_reg_clobber(state, constraint->u.blob);
-
 		piece = triple(state, OP_PIECE, &void_type, def, 0);
 		piece->u.cval = i;
 		LHS(def, i) = piece;
 		flatten(state, first, piece);
-		free_triple(state, constraint);
 	}
 }
 
@@ -12195,11 +12258,18 @@ static void least_conflict(struct compile_state *state,
 	struct triple_reg_set *set;
 	size_t count;
 
+#if 0
+#define HI() fprintf(stderr, "%-10p(%-15s) %d\n", ins, tops(ins->op), __LINE__)
+#else
+#define HI()
+#endif
+
 #warning "FIXME handle instructions with left hand sides..."
 	/* Only instructions that introduce a new definition
 	 * can be the conflict instruction.
 	 */
 	if (!triple_is_def(state, ins)) {
+HI();
 		return;
 	}
 
@@ -12216,11 +12286,13 @@ static void least_conflict(struct compile_state *state,
 			}
 		}
 		if (!edge && (lr != conflict->ref_range)) {
+HI();
 			return;
 		}
 		count++;
 	}
 	if (count <= 1) {
+HI();
 		return;
 	}
 
@@ -12234,6 +12306,7 @@ static void least_conflict(struct compile_state *state,
 		}
 	}
 	if (!set && (conflict->ref_range != REG_UNSET)) {
+HI();
 		return;
 	}
 
@@ -12280,6 +12353,7 @@ static void least_conflict(struct compile_state *state,
 			;
 		}
 	}
+HI();
 	return;
 }
 
@@ -12287,6 +12361,13 @@ static void find_range_conflict(struct compile_state *state,
 	struct reg_state *rstate, char *used, struct live_range *ref_range,
 	struct least_conflict *conflict)
 {
+
+#if 0
+	static void verify_blocks(struct compile_state *stae);
+	verify_blocks(state);
+	print_blocks(state, stderr);
+	print_dominators(state, stderr);
+#endif
 	/* there are 3 kinds ways conflicts can occure.
 	 * 1) the life time of 2 values simply overlap.
 	 * 2) the 2 values feed into the same instruction.
@@ -12314,10 +12395,28 @@ static void find_range_conflict(struct compile_state *state,
 	walk_variable_lifetimes(state, rstate->blocks, least_conflict, conflict);
 
 	if (!conflict->ins) {
-		internal_error(state, 0, "No conflict ins?");
+		struct live_range_edge *edge;
+		struct live_range_def *lrd;
+		fprintf(stderr, "edges:\n");
+		for(edge = ref_range->edges; edge; edge = edge->next) {
+			lrd = edge->node->defs;
+			do {
+				fprintf(stderr, " %-10p(%s)", lrd->def, tops(lrd->def->op));
+				lrd = lrd->next;
+			} while(lrd != edge->node->defs);
+			fprintf(stderr, "|\n");
+		}
+		fprintf(stderr, "range:\n");
+		lrd = ref_range->defs;
+		do {
+			fprintf(stderr, " %-10p(%s)", lrd->def, tops(lrd->def->op));
+			lrd = lrd->next;
+		} while(lrd != ref_range->defs);
+		fprintf(stderr,"\n");
+		internal_error(state, ref_range->defs->def, "No conflict ins?");
 	}
 	if (!conflict->live) {
-		internal_error(state, 0, "No conflict live?");
+		internal_error(state, ref_range->defs->def, "No conflict live?");
 	}
 	return;
 }
@@ -13899,7 +13998,9 @@ static void verify_uses(struct compile_state *state)
 		struct triple **expr;
 		expr = triple_rhs(state, ins, 0);
 		for(; expr; expr = triple_rhs(state, ins, expr)) {
-			for(set = *expr?(*expr)->use:0; set; set = set->next) {
+			struct triple *rhs;
+			rhs = *expr;
+			for(set = rhs?rhs->use:0; set; set = set->next) {
 				if (set->member == ins) {
 					break;
 				}
@@ -13910,7 +14011,9 @@ static void verify_uses(struct compile_state *state)
 		}
 		expr = triple_lhs(state, ins, 0);
 		for(; expr; expr = triple_lhs(state, ins, expr)) {
-			for(set =  *expr?(*expr)->use:0; set; set = set->next) {
+			struct triple *lhs;
+			lhs = *expr;
+			for(set =  lhs?lhs->use:0; set; set = set->next) {
 				if (set->member == ins) {
 					break;
 				}
@@ -14140,6 +14243,7 @@ static void print_op_asm(struct compile_state *state,
 		}
 	}
 	lhs = i;
+	fprintf(fp, "#ASM\n");
 	fputc('\t', fp);
 	for(ptr = info->str; *ptr; ptr++) {
 		char *next;
@@ -14165,9 +14269,9 @@ static void print_op_asm(struct compile_state *state,
 		piece = (param < lhs)? LHS(ins, param) : RHS(ins, param - lhs);
 		fprintf(fp, "%s", 
 			arch_reg_str(ID_REG(piece->id)));
-		ptr = next;
+		ptr = next -1;
 	}
-	fputc('\n', fp);
+	fprintf(fp, "\n#NOT ASM\n");
 }
 
 
diff --git a/util/romcc/tests/simple_test22.c b/util/romcc/tests/simple_test22.c
index 247369b80b..81d2ed008d 100644
--- a/util/romcc/tests/simple_test22.c
+++ b/util/romcc/tests/simple_test22.c
@@ -21,7 +21,7 @@ static struct syscall_result syscall0(unsigned long nr)
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr));
 	return syscall_return(res);
 }
@@ -31,7 +31,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1));
 	return syscall_return(res);
 	
@@ -42,7 +42,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2));
 	return syscall_return(res);
 	
@@ -55,7 +55,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
 	return syscall_return(res);
 	
@@ -67,7 +67,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
 	return syscall_return(res);
 	
@@ -79,7 +79,7 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), 
 		"S" (arg4), "D" (arg5));
 	return syscall_return(res);
diff --git a/util/romcc/tests/simple_test30.c b/util/romcc/tests/simple_test30.c
index fc21fc6833..6582a91c1a 100644
--- a/util/romcc/tests/simple_test30.c
+++ b/util/romcc/tests/simple_test30.c
@@ -21,7 +21,7 @@ static struct syscall_result syscall0(unsigned long nr)
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr));
 	return syscall_return(res);
 }
@@ -31,7 +31,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1));
 	return syscall_return(res);
 	
@@ -42,7 +42,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2));
 	return syscall_return(res);
 	
@@ -55,7 +55,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
 	return syscall_return(res);
 	
@@ -67,7 +67,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
 	return syscall_return(res);
 	
@@ -79,7 +79,7 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
 	long res;
 	asm volatile(
 		"int $0x80"
-		: "a" (res)
+		: "=a" (res)
 		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), 
 		"S" (arg4), "D" (arg5));
 	return syscall_return(res);
diff --git a/util/romcc/tests/simple_test32.c b/util/romcc/tests/simple_test32.c
new file mode 100644
index 0000000000..bd6947a2ba
--- /dev/null
+++ b/util/romcc/tests/simple_test32.c
@@ -0,0 +1,35 @@
+void main(void)
+{
+	unsigned long addr, start, stop;
+	start = 0x00100000;
+	stop = 0x00180000;
+	
+
+	for(addr = start; addr < stop ;) {
+		unsigned char ch;
+		const char *str = "\r";
+		while((ch = *str++) != '\0') {
+			while(__builtin_inb(0x3f))
+				;
+			__builtin_outb(ch, 0x3f8);
+			
+			while(__builtin_inb(0x3f))
+				;
+		}
+		asm (
+			"jmp 2f\n\t"
+			"1:\n\t"
+			"testl  $0xffff, %0\n\t"
+			"jz	3f\n\t"
+			"movnti %0, (%0)\n\t"
+			"add $4, %0\n\t"
+			"2:\n\t"
+			"cmp %2, %0\n\t"
+			"jl 1b\n\t"
+			"3:\n\t"
+			: "=b" (addr)		   /* outputs */
+			: "0" (addr), "r" (stop)   /* intputs */
+			: /* clobbers */
+			);
+	};
+}