diff options
| author | Rob Barnes <robbarnes@google.com> | 2020-08-14 15:23:05 -0600 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-08-27 21:41:30 +0000 |
| commit | 8cc80d5e50c9382fb04041d7af9c1b59bba0184f (patch) | |
| tree | ed2060369ef2e5f39328bd72bdfd7c3cd3ff4809 | |
| parent | a2e431331cbbad167efa1524e42a863a49e03a14 (diff) | |
util: Add Picasso and Pollock platforms to spd_tools
PCO = Picasso
PLK = Pollock
BUG=b:162939176
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | util/spd_tools/ddr4/README.md | 15 | ||||
| -rw-r--r-- | util/spd_tools/ddr4/gen_spd.go | 4 |
2 files changed, 11 insertions, 8 deletions
diff --git a/util/spd_tools/ddr4/README.md b/util/spd_tools/ddr4/README.md index 31e326d442..7921f48a5d 100644 --- a/util/spd_tools/ddr4/README.md +++ b/util/spd_tools/ddr4/README.md @@ -1,14 +1,13 @@ # DDR4 SPD tools README -Tools for generating SPD files for DDR4 memory used in memory down -configurations on Intel Tiger Lake (TGL) based -platforms. These tools generate SPDs following JESD79-4C +Tools for generating SPD files for DDR4 memory used in platforms with +memory down configuration. These tools generate SPDs following JESD79-4C and Jedec 4.1.2.L-5 R29 v103 specifications. -There are two tools provided that assist TGL based mainboards -to generate SPDs and Makefile to integrate these SPDs in coreboot -build. These tools can also be used to allocate DRAM IDs (configure -DRAM hardware straps) for any DDR4 memory part used by the board. +There are two tools provided that assist with generating SPDs and Makefiles +to integrate in coreboot build. These tools can also be used to allocate +DRAM IDs (configure DRAM hardware straps) for any DDR4 memory part used +by the board. * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, @@ -31,7 +30,7 @@ This program takes as input: attributes as per the datasheet. This is the list of all known DDR4 memory parts irrespective of their usage on the board. * SoC platform name for which the SPDs are being generated. Currently - supported platform names are `TGL`. + supported platform names are `TGL`, `PCO` and `PLK`. Input JSON file requires the following two fields for every memory part: * `name`: Name of the memory part diff --git a/util/spd_tools/ddr4/gen_spd.go b/util/spd_tools/ddr4/gen_spd.go index 0462fd5056..831cddf824 100644 --- a/util/spd_tools/ddr4/gen_spd.go +++ b/util/spd_tools/ddr4/gen_spd.go @@ -29,10 +29,14 @@ const ( SPDManifestFileName = "spd_manifest.generated.txt" PlatformTGL = 0 + PlatformPCO = 1 + PlatformPLK = 2 ) var platformMap = map[string]int { "TGL": PlatformTGL, + "PCO": PlatformPCO, + "PLK": PlatformPLK, } var currPlatform int |