dram/ddr3: Use the same naming convention as DDR4

Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 39 insertions, 39 deletions

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index 8d2752b15c..09a4e7ff9f 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -365,7 +365,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd)
 	memcpy(dimm->part_number, &spd[128], 16);
 	printram("  Part number        : %s\n", dimm->part_number);
 
-	memcpy(dimm->serial, &spd[SPD_DIMM_SERIAL_NUM], SPD_DIMM_SERIAL_LEN);
+	memcpy(dimm->serial, &spd[SPD_DDR3_SERIAL_NUM], SPD_DDR3_SERIAL_LEN);
 
 	return ret;
 }
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 65977b49c1..c4fd253efd 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -27,12 +27,12 @@
  *
  * @{
  */
-#define SPD_DIMM_MOD_ID1	117
-#define SPD_DIMM_MOD_ID2	118
-#define SPD_DIMM_SERIAL_NUM	122
-#define SPD_DIMM_SERIAL_LEN	4
-#define SPD_DIMM_PART_NUM	128
-#define SPD_DIMM_PART_LEN	18
+#define SPD_DDR3_MOD_ID1	117
+#define SPD_DDR3_MOD_ID2	118
+#define SPD_DDR3_SERIAL_NUM	122
+#define SPD_DDR3_SERIAL_LEN	4
+#define SPD_DDR3_PART_NUM	128
+#define SPD_DDR3_PART_LEN	18
 /** @} */
 
 /* Byte 3 [3:0]: DDR3 Module type information */
@@ -145,7 +145,7 @@ struct dimm_attr_ddr3_st {
 	/* ASCII part number - NULL terminated */
 	u8 part_number[17];
 	/* Serial number */
-	u8 serial[SPD_DIMM_SERIAL_LEN];
+	u8 serial[SPD_DDR3_SERIAL_LEN];
 };
 
 enum ddr3_xmp_profile {
diff --git a/src/northbridge/intel/gm45/raminit_meminfo.c b/src/northbridge/intel/gm45/raminit_meminfo.c
index c2c7f510d8..9fd4065ffc 100644
--- a/src/northbridge/intel/gm45/raminit_meminfo.c
+++ b/src/northbridge/intel/gm45/raminit_meminfo.c
@@ -24,14 +24,14 @@ static u8 get_dimm_mod_type(const sysinfo_t *sysinfo, const int idx)
 static void ddr3_read_ids(const sysinfo_t *sysinfo, struct dimm_info *dimm, const int idx)
 {
 	const u8 addr = sysinfo->spd_map[idx];
-	for (int k = 0; k < SPD_DIMM_SERIAL_LEN; k++) {
-		dimm->serial[k] = smbus_read_byte(addr, SPD_DIMM_SERIAL_NUM + k);
+	for (int k = 0; k < SPD_DDR3_SERIAL_LEN; k++) {
+		dimm->serial[k] = smbus_read_byte(addr, SPD_DDR3_SERIAL_NUM + k);
 	}
-	for (int k = 0; k < SPD_DIMM_PART_LEN; k++) {
-		dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DIMM_PART_NUM + k);
+	for (int k = 0; k < SPD_DDR3_PART_LEN; k++) {
+		dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DDR3_PART_NUM + k);
 	}
-	dimm->mod_id = (smbus_read_byte(addr, SPD_DIMM_MOD_ID2) << 8) |
-		       (smbus_read_byte(addr, SPD_DIMM_MOD_ID1) << 0);
+	dimm->mod_id = (smbus_read_byte(addr, SPD_DDR3_MOD_ID2) << 8) |
+		       (smbus_read_byte(addr, SPD_DDR3_MOD_ID1) << 0);
 }
 
 static u32 get_mem_clock_mt(const int clock_index)
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index e7e9b634c8..7af21f578a 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -219,14 +219,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 				dimm->dimm_num = slot;
 				dimm->bank_locator = ch * 2;
 				memcpy(dimm->serial,
-					&pei_data->spd_data[ch][slot][SPD_DIMM_SERIAL_NUM],
-					SPD_DIMM_SERIAL_LEN);
+					&pei_data->spd_data[ch][slot][SPD_DDR3_SERIAL_NUM],
+					SPD_DDR3_SERIAL_LEN);
 				memcpy(dimm->module_part_number,
-					&pei_data->spd_data[ch][slot][SPD_DIMM_PART_NUM],
-					SPD_DIMM_PART_LEN);
+					&pei_data->spd_data[ch][slot][SPD_DDR3_PART_NUM],
+					SPD_DDR3_PART_LEN);
 				dimm->mod_id =
-					(pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID2] << 8) |
-					(pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID1] & 0xff);
+					(pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID2] << 8) |
+					(pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID1] & 0xff);
 				dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
 				dimm->bus_width = MEMORY_BUS_WIDTH_64;
 				dimm_cnt++;
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 7109e46da0..d97ab2a8ac 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -252,14 +252,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 				dimm->dimm_num = d_num;
 				dimm->bank_locator = ch * 2;
 				memcpy(dimm->serial,
-					&pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM],
-					SPD_DIMM_SERIAL_LEN);
+					&pei_data->spd_data[index][SPD_DDR3_SERIAL_NUM],
+					SPD_DDR3_SERIAL_LEN);
 				memcpy(dimm->module_part_number,
-					&pei_data->spd_data[index][SPD_DIMM_PART_NUM],
-					SPD_DIMM_PART_LEN);
+					&pei_data->spd_data[index][SPD_DDR3_PART_NUM],
+					SPD_DDR3_PART_LEN);
 				dimm->mod_id =
-					(pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
-					(pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
+					(pei_data->spd_data[index][SPD_DDR3_MOD_ID2] << 8) |
+					(pei_data->spd_data[index][SPD_DDR3_MOD_ID1] & 0xff);
 				dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
 				dimm->bus_width = MEMORY_BUS_WIDTH_64;
 				dimm_cnt++;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2a4eae5bd5..8a8bd8310b 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -142,7 +142,7 @@ static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only)
 {
 	int j;
 	if (id_only) {
-		for (j = SPD_DIMM_MOD_ID1; j < 128; j++)
+		for (j = SPD_DDR3_MOD_ID1; j < 128; j++)
 			(*spd)[j] = smbus_read_byte(addr, j);
 	} else {
 		for (j = 0; j < SPD_SIZE_MAX_DDR3; j++)
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index cad86ba51e..8d3c4023c8 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -467,14 +467,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 			dimm->dimm_num = 0;
 			dimm->bank_locator = i * 2;
 			memcpy(dimm->serial,				/* bytes 122-125 */
-				&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
-				sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
+				&pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM],
+				sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN);
 			memcpy(dimm->module_part_number,		/* bytes 128-145 */
-				&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
-				sizeof(uint8_t) * SPD_DIMM_PART_LEN);
+				&pei_data->spd_data[0][SPD_DDR3_PART_NUM],
+				sizeof(uint8_t) * SPD_DDR3_PART_LEN);
 			dimm->mod_id =					/* bytes 117/118 */
-				(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
-				(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
+				(pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) |
+				(pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF);
 			dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
 			dimm->bus_width = MEMORY_BUS_WIDTH_64;
 			dimm_cnt++;
@@ -491,14 +491,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 			dimm->dimm_num = 1;
 			dimm->bank_locator = i * 2;
 			memcpy(dimm->serial,				/* bytes 122-125 */
-				&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
-				sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
+				&pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM],
+				sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN);
 			memcpy(dimm->module_part_number,		/* bytes 128-145 */
-				&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
-				sizeof(uint8_t) * SPD_DIMM_PART_LEN);
+				&pei_data->spd_data[0][SPD_DDR3_PART_NUM],
+				sizeof(uint8_t) * SPD_DDR3_PART_LEN);
 			dimm->mod_id =					/* bytes 117/118 */
-				(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
-				(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
+				(pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) |
+				(pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF);
 			dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
 			dimm->bus_width = MEMORY_BUS_WIDTH_64;
 			dimm_cnt++;