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authorSean Rhodes <sean@starlabs.systems>2022-05-30 10:57:11 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-06-20 12:09:44 +0000
commit8a4f0768948a7f32aeb7dee495e7c85e650597fd (patch)
treec7a6657ced5d34fc81dd4c7713586689d63f8766
parentfe97c77cab5f91bef5890257e56a63f8aa027cd8 (diff)
mb/starlabs/lite/glkr: Organise USB ports by hardware port
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/starlabs/lite/variants/glkr/devicetree.cb15
1 files changed, 7 insertions, 8 deletions
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
index ca6ce1c6ad..1b4ddce3b4 100644
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -89,22 +89,21 @@ chip soc/intel/apollolake
### USB 2.0 Devices
# Motherboard USB Type C
register "usb2_port[0]" = "PORT_EN(OC1)"
+ register "usb3_port[1]" = "PORT_EN(OC1)"
+
# Motherboard USB 3.0
register "usb2_port[1]" = "PORT_EN(OC0)"
+ register "usb3_port[0]" = "PORT_EN(OC0)"
+
# Daughterboard USB 3.0
register "usb2_port[3]" = "PORT_EN(OC1)"
+
# Daughterboard SD Card
register "usb2_port[5]" = "PORT_EN(OC_SKIP)"
+ register "usb3_port[3]" = "PORT_EN(OC1)"
+
# Bluetooth
register "usb2_port[6]" = "PORT_EN(OC_SKIP)"
-
- ### USB 3.0 Devices
- # Motherboard USB 3.0
- register "usb3_port[0]" = "PORT_EN(OC0)"
- # Motherboard USB Type C
- register "usb3_port[1]" = "PORT_EN(OC1)"
- # Daughterboard USB 3.0
- register "usb3_port[3]" = "PORT_EN(OC1)"
end
device pci 15.1 off end # XDCI
device pci 16.0 off end # I2C0