diff options
| author | Dave Frodin <dave.frodin@se-eng.com> | 2015-01-19 15:58:24 -0700 |
|---|---|---|
| committer | Dave Frodin <dave.frodin@se-eng.com> | 2015-02-18 18:55:56 +0100 |
| commit | 891f71a541fc036bd7de892d2eabd7df23bcecbb (patch) | |
| tree | 3d24848335df84a72f7be28a888e0676d36b15d1 | |
| parent | 452efc23b94f66e89c6204bc6d3037fd4ed28e63 (diff) | |
amd/00730F01: Move SteppeEagle specific settings to northbridge
These settings are specific to the SteppeEagle SOC and should
be made in its northbridge code rather than the CPU code.
Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
| -rw-r--r-- | src/cpu/amd/pi/amd_late_init.c | 14 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 16 |
2 files changed, 16 insertions, 14 deletions
diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 46116ca4bd..4b08d1bf4f 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -34,20 +34,6 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); -#if (1) /* NORTHBRIDGE_00730F01 */ - device_t dev; - u32 value; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); -#endif - if (!acpi_s3_resume_allowed()) return; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 4ffa5110fa..b59ff6c84c 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -635,9 +635,25 @@ static const struct pci_driver family10_northbridge __pci_driver = { .device = PCI_DEVICE_ID_AMD_10H_NB_HT, }; +static void fam16_finalize(void *chip_info) +{ + device_t dev; + u32 value; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); +} + struct chip_operations northbridge_amd_pi_00730F01_ops = { CHIP_NAME("AMD FAM16 Northbridge") .enable_dev = 0, + .final = fam16_finalize, }; static void domain_read_resources(device_t dev) |