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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-07-26 17:29:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-27 16:04:56 +0000 |
| commit | 87f08bea11ecabc721e80d553ff8173c77ae19ab (patch) | |
| tree | 46ebff74793831b6129c72f829ce966e874cd296 | |
| parent | d22bb255b25d4a26ec8b0942f02a428b88d238fc (diff) | |
soc/amd/noncar/memlayout_x86.ld: Conditionally add fspm region
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e75f29a52179b72b25092f0ffdfd91a182d6648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index c435cc5eae..42323f51bf 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -97,7 +97,11 @@ SECTIONS _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); BOOTBLOCK(BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) + +#if CONFIG(PLATFORM_USES_FSP2_0) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) +#endif + #if CONFIG(VBOOT_SEPARATE_VERSTAGE) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif |