soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs

List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb

RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2

Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 42 insertions, 21 deletions

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 12cd47561a..51b781c619 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -40,39 +40,44 @@ chip soc/intel/alderlake
 	register "PrmrrSize" = "0"
 
 	# Enable PCH PCIE RP 5 using CLK 2
-	register "PcieRpEnable[4]" = "1"
+	register "PchPcieRpEnable[4]" = "1"
 	register "PcieClkSrcClkReq[2]" = "2"
 	register "PcieClkSrcUsage[2]" = "0x4"
 	register "PcieRpClkReqDetect[4]" = "1"
 
 	# Enable PCH PCIE RP 6 using CLK 5
-	register "PcieRpEnable[5]" = "1"
+	register "PchPcieRpEnable[5]" = "1"
 	register "PcieClkSrcClkReq[5]" = "5"
 	register "PcieClkSrcUsage[5]" = "0x5"
 	register "PcieRpClkReqDetect[5]" = "1"
 
 	# Enable PCH PCIE RP 8 using CLK 6
-	register "PcieRpEnable[7]" = "1"
+	register "PchPcieRpEnable[7]" = "1"
 	register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6
 	register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK
 	register "PcieRpClkReqDetect[6]" = "1"
 
 	# Enable PCH PCIE RP 9 using CLK 1
-	register "PcieRpEnable[8]" = "1"
+	register "PchPcieRpEnable[8]" = "1"
 	register "PcieClkSrcClkReq[1]" = "1"
 	register "PcieClkSrcUsage[1]" = "0x8"
 	register "PcieRpClkReqDetect[8]" = "1"
 
 	# Enable PCH PCIE RP 11 for optane
-	register "PcieRpEnable[10]" = "1"
+	register "PchPcieRpEnable[10]" = "1"
 	# Hybrid storage mode
 	register "HybridStorageMode" = "1"
 
-	# Enable CPU PCIE RP 1 using PEG CLK 0
+	# Enable CPU PCIE RP 1 using CLK 0
+	register "CpuPcieRpEnable[0]" = "1"
 	register "PcieClkSrcUsage[0]" = "0x40"
 
-	# Enable PCU PCIE PEG Slot 1 and 2
+	# Enable CPU PCIE RP 2 using CLK 3
+	register "CpuPcieRpEnable[1]" = "1"
 	register "PcieClkSrcUsage[3]" = "0x41"
+
+	# Enable CPU PCIE RP 3 using CLK 4
+	register "CpuPcieRpEnable[2]" = "1"
 	register "PcieClkSrcUsage[4]" = "0x42"
 
 	# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
@@ -177,10 +182,12 @@ chip soc/intel/alderlake
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # PEG10
 		device pci 02.0 on  end # Graphics
 		device pci 04.0 on  end # DPTF
 		device pci 05.0 on  end # IPU
 		device pci 06.0 on  end # PEG60
+		device pci 06.2 on  end # PEG62
 		device pci 07.0 on  end # TBT_PCIe0
 		device pci 07.1 on  end # TBT_PCIe1
 		device pci 07.2 on  end # TBT_PCIe2
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c73df5019d..8009a42ae1 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -119,10 +119,18 @@ config HEAP_SIZE
 	hex
 	default 0x10000
 
-config MAX_ROOT_PORTS
+config MAX_PCH_ROOT_PORTS
 	int
 	default 12
 
+config MAX_CPU_ROOT_PORTS
+	int
+	default 3
+
+config MAX_ROOT_PORTS
+	int
+	default MAX_PCH_ROOT_PORTS
+
 config MAX_PCIE_CLOCKS
 	int
 	default 12
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 38d9671f60..8e59c9ad5c 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -118,9 +118,12 @@ struct soc_intel_alderlake_config {
 	uint8_t PchHdaIDispLinkFrequency;
 	uint8_t PchHdaIDispCodecDisconnect;
 
-	/* PCIe Root Ports */
-	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
-	uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
+	/* CPU PCIe Root Ports */
+	uint8_t CpuPcieRpEnable[CONFIG_MAX_CPU_ROOT_PORTS];
+
+	/* PCH PCIe Root Ports */
+	uint8_t PchPcieRpEnable[CONFIG_MAX_PCH_ROOT_PORTS];
+	uint8_t PcieRpHotPlug[CONFIG_MAX_PCH_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
@@ -130,7 +133,7 @@ struct soc_intel_alderlake_config {
 	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
 
 	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
-	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];
 
 	/* PCIe RP L1 substate */
 	enum L1_substates_control {
@@ -138,13 +141,13 @@ struct soc_intel_alderlake_config {
 		L1_SS_DISABLED,
 		L1_SS_L1_1,
 		L1_SS_L1_2,
-	} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+	} PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
 
 	/* PCIe LTR: Enable (1) / Disable (0) */
-	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS];
 
 	/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
-	uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_PCH_ROOT_PORTS];
 
 	/* Gfx related */
 	enum {
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 6de8649cb8..35f7a3c2e2 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -270,7 +270,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Enable Hybrid storage auto detection */
 	params->HybridStorageMode = config->HybridStorageMode;
 
-	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
+	for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) {
 		params->PcieRpL1Substates[i] =
 			get_l1_substate_control(config->PcieRpL1Substates[i]);
 		params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 7e842a200c..a615f0bc6a 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -41,8 +41,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		/* Set CpuRatio to match existing MSR value */
 		m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
 
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
+	for (i = 0; i < ARRAY_SIZE(config->PchPcieRpEnable); i++) {
+		if (config->PchPcieRpEnable[i])
 			mask |= (1 << i);
 	}
 	m_cfg->PcieRpEnableMask = mask;
@@ -155,9 +155,12 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	/* Skip CPU replacement check */
 	m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
 
-	/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
-	dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
-	m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev);
+	mask = 0;
+	for (i = 0; i < ARRAY_SIZE(config->CpuPcieRpEnable); i++) {
+		if (config->CpuPcieRpEnable[i])
+			mask |= (1 << i);
+	}
+	m_cfg->CpuPcieRpEnableMask = mask;
 
 	m_cfg->TmeEnable = CONFIG(INTEL_TME);