Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELL

To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL.

Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for
CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However,
there seems to be no particular reason on those platforms. We've dropped
the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that
VBOOT_VBNV_FLASH can be enabled.

VBOOT_VBNV_FLASH is enabled for the following boards:

- facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the
  FW_MAIN_A(CBFS) size reduced by 0x2000.
- google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM.

[1] https://issuetracker.google.com/issues/235293589
[2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08
    ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config")

BUG=b:235293589
TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected)
TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a
TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a

Change-Id: I46542c2887b254f59245f20b8642b023a7871708
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>

7 files changed, 10 insertions, 10 deletions

diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig
index 15528642e0..1218102406 100644
--- a/src/mainboard/facebook/fbg1701/Kconfig
+++ b/src/mainboard/facebook/fbg1701/Kconfig
@@ -24,7 +24,7 @@ config USE_VENDORCODE_ELTAN
 
 if VBOOT
 
-config VBOOT_VBNV_CMOS
+config VBOOT_VBNV_FLASH
 	default y
 
 config VBOOT_SLOTS_RW_A
diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd
index 172256f7ac..a00c0c9d92 100644
--- a/src/mainboard/facebook/fbg1701/vboot-rw.fmd
+++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd
@@ -1,12 +1,13 @@
 FLASH@0xff800000 8M {
 	SI_BIOS@0x200000 0x600000 {
-		MISC_RW@0x0 0x08000 {
-			RW_MRC_CACHE@0 0x08000
+		MISC_RW@0x0 0x0a000 {
+			RW_MRC_CACHE@0x0 0x08000
+			RW_NVRAM@0x8000 0x2000
 		}
-		RW_SECTION_A@0x08000 0x558000 {
+		RW_SECTION_A@0x0a000 0x556000 {
 			VBLOCK_A@0x0 0x10000
 			RW_FWID_A@0x10000 0x40
-			FW_MAIN_A(CBFS)@0x10040 0x547FC0
+			FW_MAIN_A(CBFS)@0x10040 0x545FC0
 		}
 		WP_RO@0x560000 0x0a0000 {
 			RO_SECTION@0x0000 0xa0000 {
diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index ac679c765f..710ecc2c06 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -57,7 +57,7 @@ if BOARD_GOOGLE_BASEBOARD_CYAN
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_LID_SWITCH
-	select VBOOT_VBNV_CMOS
+	select VBOOT_VBNV_FLASH
 
 config DISPLAY_SPD_DATA
 	bool "Display Memory Serial Presence Detect Data"
diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd
index 923c8ee18a..bc9bac3344 100644
--- a/src/mainboard/google/cyan/chromeos.fmd
+++ b/src/mainboard/google/cyan/chromeos.fmd
@@ -21,7 +21,7 @@ FLASH@0xff800000 0x800000 {
 			VBLOCK_DEV@0x2000 0x2000
 		}
 		RW_VPD(PRESERVE)@0x1f8000 0x2000
-		RW_UNUSED@0x1fa000 0x6000
+		RW_NVRAM@0x1fa000 0x6000
 		SMMSTORE(PRESERVE)@0x200000 0x40000
 		RW_LEGACY(CBFS)@0x240000 0x1c0000
 		WP_RO@0x400000 0x200000 {
diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig
index 144ba5aaa3..b15984f448 100644
--- a/src/mainboard/intel/strago/Kconfig
+++ b/src/mainboard/intel/strago/Kconfig
@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_LID_SWITCH
-	select VBOOT_VBNV_CMOS
+	select VBOOT_VBNV_FLASH
 
 config MAINBOARD_DIR
 	default "intel/strago"
diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd
index 923c8ee18a..bc9bac3344 100644
--- a/src/mainboard/intel/strago/chromeos.fmd
+++ b/src/mainboard/intel/strago/chromeos.fmd
@@ -21,7 +21,7 @@ FLASH@0xff800000 0x800000 {
 			VBLOCK_DEV@0x2000 0x2000
 		}
 		RW_VPD(PRESERVE)@0x1f8000 0x2000
-		RW_UNUSED@0x1fa000 0x6000
+		RW_NVRAM@0x1fa000 0x6000
 		SMMSTORE(PRESERVE)@0x200000 0x40000
 		RW_LEGACY(CBFS)@0x240000 0x1c0000
 		WP_RO@0x400000 0x200000 {
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index c35fa7473d..4d3d4df6ea 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_X86
-	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select SUPPORT_CPU_UCODE_IN_CBFS