diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-04-15 10:20:41 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-10-07 20:24:53 +0000 |
| commit | 7d904cb7c64df0f156dc7f79cbfd4ffc57deeb29 (patch) | |
| tree | a86f51a90bf39b0cf032cb5fcf4efdf6e53b1d64 | |
| parent | b6974ab13deccb89d8fa749a37ad97fc951eddc8 (diff) | |
soc/intel/alderlake: Hook up PCIe Power Management to option API
Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the
option API.
This provides users an easy way to disable power saving options
that can limit performance.
Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81906
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8c4c29122d..a59be35dd2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -529,9 +529,12 @@ static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, const struct pcie_rp_config *rp_cfg, unsigned int index) { - s_cfg->PcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM); - s_cfg->PcieRpAspm[index] = adl_aspm_control_to_upd(rp_cfg->pcie_rp_aspm); - s_cfg->PcieRpL1Substates[index] = adl_l1ss_control_to_upd(rp_cfg->PcieRpL1Substates); + s_cfg->PcieRpEnableCpm[index] = + get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->PcieRpAspm[index] = + adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->PcieRpL1Substates[index] = + adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); } /* @@ -551,11 +554,14 @@ static void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, const struct pcie_rp_config *rp_cfg, unsigned int index) { - s_cfg->CpuPcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM); - s_cfg->CpuPcieClockGating[index] = CONFIG(PCIEXP_CLK_PM); - s_cfg->CpuPciePowerGating[index] = CONFIG(PCIEXP_CLK_PM); - s_cfg->CpuPcieRpAspm[index] = adl_aspm_control_to_upd(rp_cfg->pcie_rp_aspm); - s_cfg->CpuPcieRpL1Substates[index] = adl_l1ss_control_to_upd(rp_cfg->PcieRpL1Substates); + bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; + s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; + s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; + s_cfg->CpuPcieRpAspm[index] = + adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->CpuPcieRpL1Substates[index] = + adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); } /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL |