diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-07-14 13:18:29 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-15 14:03:57 +0000 |
| commit | 7d3e57d7a39de2122cbb6102fbc17c3d32e590ef (patch) | |
| tree | 1cdaac042b3a96500f81fda2290bf6c4f6e637fc | |
| parent | 7b8d11b1869dfcf5e8cae464d29504438b87f964 (diff) | |
soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDs
Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and
SOC_INTEL_CRASHLOG is selected by the SoC user.
Change-Id: Ibcd0259da86c8d9853e6cc4983675ac97df46c2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index dca84cc725..15a11cdc46 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -197,10 +197,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TmeEnable = CONFIG(INTEL_TME); /* crashLog config */ - if (CONFIG(SOC_INTEL_CRASHLOG)) { - m_cfg->CpuCrashLogDevice = 1; - m_cfg->CpuCrashLogEnable = 1; - } + m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); + m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |