summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDavid Wu <david_wu@quanta.corp-partner.google.com>2022-01-21 19:45:54 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-27 14:46:21 +0000
commit79effad1fc743f43ffd37b592b46b2ac94a6a933 (patch)
treeeba0d000c28dd4c14fa5256730b7dda4c35e7f8e
parent2bff1545985c9ada3adc78c23ddee259c17b4847 (diff)
mb/google/brya/variants/volmar: Init devicetree for volmar
Init basic override devicetree based on schematics BUG=b:211891086 TEST=FW_NAME="volmar" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I40b364e3df2f04a6b828f4f288667b96b6e0bd22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
-rw-r--r--src/mainboard/google/brya/Kconfig.name2
-rw-r--r--src/mainboard/google/brya/variants/volmar/Makefile.inc2
-rw-r--r--src/mainboard/google/brya/variants/volmar/fw_config.c87
-rw-r--r--src/mainboard/google/brya/variants/volmar/overridetree.cb389
-rw-r--r--src/mainboard/google/brya/variants/volmar/variant.c10
5 files changed, 488 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 26c90da03d..19930592e1 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -150,6 +150,8 @@ config BOARD_GOOGLE_VELL
config BOARD_GOOGLE_VOLMAR
bool "-> Volmar"
select BOARD_GOOGLE_BASEBOARD_BRYA
+ select DRIVERS_I2C_MAX98373
+ select DRIVERS_I2C_NAU8825
config BOARD_GOOGLE_BANSHEE
bool "-> Banshee"
diff --git a/src/mainboard/google/brya/variants/volmar/Makefile.inc b/src/mainboard/google/brya/variants/volmar/Makefile.inc
index d38141ca24..9ea19ded56 100644
--- a/src/mainboard/google/brya/variants/volmar/Makefile.inc
+++ b/src/mainboard/google/brya/variants/volmar/Makefile.inc
@@ -4,3 +4,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/volmar/fw_config.c b/src/mainboard/google/brya/variants/volmar/fw_config.c
new file mode 100644
index 0000000000..375dca2e2a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/volmar/fw_config.c
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
+ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+ PAD_NC(GPP_R4, NONE),
+ PAD_NC(GPP_R5, NONE),
+ PAD_NC(GPP_R6, NONE),
+ PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+ PAD_NC(GPP_R0, NONE),
+ PAD_NC(GPP_R1, NONE),
+ PAD_NC(GPP_R2, NONE),
+ PAD_NC(GPP_R3, NONE),
+ PAD_NC(GPP_S0, NONE),
+ PAD_NC(GPP_S1, NONE),
+ PAD_NC(GPP_S2, NONE),
+ PAD_NC(GPP_S3, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+ PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
+ PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
+ PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
+ PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
+ PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
+ PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
+ PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
+ PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+ PAD_NC(GPP_VGPIO_30, NONE),
+ PAD_NC(GPP_VGPIO_31, NONE),
+ PAD_NC(GPP_VGPIO_32, NONE),
+ PAD_NC(GPP_VGPIO_33, NONE),
+ PAD_NC(GPP_VGPIO_34, NONE),
+ PAD_NC(GPP_VGPIO_35, NONE),
+ PAD_NC(GPP_VGPIO_36, NONE),
+ PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+ if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+ printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+ gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+ gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+ gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+ return;
+ }
+
+ if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S))) {
+ printk(BIOS_INFO, "Configure audio over I2S with MAX98373 NAU88L25B.\n");
+ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+ gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+ printk(BIOS_INFO, "Enabling BT offload\n");
+ gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+ } else {
+ printk(BIOS_INFO, "Disabling BT offload\n");
+ gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+ }
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb
index 4f2c04a57a..80c1fd6261 100644
--- a/src/mainboard/google/brya/variants/volmar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb
@@ -1,6 +1,391 @@
+fw_config
+ field DB_USB 0 3
+ option USB_ABSENT 0
+ option USB3_PS8815 1
+ end
+ field KB_BL 4 4
+ option KB_BL_ABSENT 0
+ option KB_BL_PRESENT 1
+ end
+ field AUDIO 5 7
+ option AUDIO_UNKNOWN 0
+ option MAX98373_NAU88L25B_I2S 1
+ end
+end
chip soc/intel/alderlake
+ register "SaGv" = "SaGv_Enabled"
+
+ register "TcssAuxOri" = "1"
+ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
+
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
+
+ # FIVR configurations are disabled since the board doesn't have V1p05 and Vnn
+ # bypass rails implemented.
+ register "ext_fivr_settings" = "{
+ .configure_ext_fivr = 1,
+ }"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C3 | TouchScreen |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[1] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 600,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ }"
+
+ device domain 0 on
+ device ref dtt on
+ chip drivers/intel/dptf
+ ## sensor information
+ register "options.tsr[0].desc" = ""DRAM""
+ register "options.tsr[1].desc" = ""Soc""
+ register "options.tsr[2].desc" = ""Charger""
+
+ # TODO: below values are initial reference values only
+ ## Active Policy
+ register "policies.active" = "{
+ [0] = {
+ .target = DPTF_CPU,
+ .thresholds = {
+ TEMP_PCT(85, 90),
+ TEMP_PCT(75, 80),
+ TEMP_PCT(68, 70),
+ TEMP_PCT(62, 60),
+ TEMP_PCT(55, 50),
+ TEMP_PCT(50, 40),
+ TEMP_PCT(40, 30),
+ }
+ },
+ [1] = {
+ .target = DPTF_TEMP_SENSOR_1,
+ .thresholds = {
+ TEMP_PCT(60, 90),
+ TEMP_PCT(55, 80),
+ TEMP_PCT(52, 70),
+ TEMP_PCT(48, 60),
+ TEMP_PCT(44, 50),
+ TEMP_PCT(40, 40),
+ TEMP_PCT(36, 30),
+ }
+ }
+ }"
+
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
+ [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
+ }"
+
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+ }"
+
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 18000,
+ .max_power = 28000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,
+ },
+ .pl2 = {
+ .min_power = 40000,
+ .max_power = 40000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,
+ }
+ }"
+
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 1700 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }
+ }"
+
+ ## Fan Performance Control (Percent, Speed, Noise, Power)
+ register "controls.fan_perf" = "{
+ [0] = { 90, 6700, 220, 2200, },
+ [1] = { 80, 5800, 180, 1800, },
+ [2] = { 70, 5000, 145, 1450, },
+ [3] = { 60, 4900, 115, 1150, },
+ [4] = { 50, 3838, 90, 900, },
+ [5] = { 40, 2904, 55, 550, },
+ [6] = { 30, 2337, 30, 300, },
+ [7] = { 20, 1608, 15, 150, },
+ [8] = { 10, 800, 10, 100, },
+ [9] = { 0, 0, 0, 50, }
+ }"
- device domain 0 on
- end
+ ## Fan options
+ register "options.fan.fine_grained_control" = "1"
+ register "options.fan.step_size" = "2"
+ device generic 0 alias dptf_policy on end
+ end
+ end
+ device ref pcie4_0 on
+ # Enable CPU PCIE RP 1 using CLK 0
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 0,
+ .clk_src = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end
+ device ref i2c0 on
+ chip drivers/i2c/nau8825
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+ register "jkdet_enable" = "1"
+ register "jkdet_pull_enable" = "0"
+ register "jkdet_pull_up" = "0"
+ register "jkdet_polarity" = "1" # ActiveLow
+ register "vref_impedance" = "2" # 125kOhm
+ register "micbias_voltage" = "6" # 2.754
+ register "sar_threshold_num" = "4"
+ register "sar_threshold[0]" = "0x0C"
+ register "sar_threshold[1]" = "0x1C"
+ register "sar_threshold[2]" = "0x38"
+ register "sar_threshold[3]" = "0x60"
+ register "sar_hysteresis" = "1"
+ register "sar_voltage" = "6"
+ register "sar_compare_time" = "0" # 500ns
+ register "sar_sampling_time" = "0" # 2us
+ register "short_key_debounce" = "2" # 100ms
+ register "jack_insert_debounce" = "7" # 512ms
+ register "jack_eject_debounce" = "7" # 512ms
+ device i2c 1a on
+ probe AUDIO MAX98373_NAU88L25B_I2S
+ end
+ end
+ chip drivers/i2c/max98373
+ register "vmon_slot_no" = "0"
+ register "imon_slot_no" = "1"
+ register "uid" = "0"
+ register "desc" = ""Right Speaker Amp""
+ register "name" = ""MAXR""
+ device i2c 31 on
+ probe AUDIO MAX98373_NAU88L25B_I2S
+ end
+ end
+ chip drivers/i2c/max98373
+ register "vmon_slot_no" = "2"
+ register "imon_slot_no" = "3"
+ register "uid" = "1"
+ register "desc" = ""Left Speaker Amp""
+ register "name" = ""MAXL""
+ device i2c 32 on
+ probe AUDIO MAX98373_NAU88L25B_I2S
+ end
+ end
+ end #I2C0
+ device ref i2c1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+ device i2c 50 on end
+ end
+ end
+ device ref i2c3 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN90FC""
+ register "generic.desc" = ""ELAN Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+ register "generic.reset_delay_ms" = "20"
+ register "generic.reset_off_delay_ms" = "1"
+ register "generic.enable_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+ register "generic.enable_delay_ms" = "6"
+ register "generic.stop_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+ register "generic.stop_off_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "generic.disable_gpio_export_in_crs" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 0x10 on end
+ end
+ end
+ device ref i2c5 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+ register "wake" = "GPE0_DW2_14"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+ register "generic.wake" = "GPE0_DW2_14"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 0x2c on end
+ end
+ end
+ device ref pcie_rp3 on
+ # Enable PCIe-to-eMMC bridge PCIE 3 using clk 4
+ register "pch_pcie_rp[PCH_RP(3)]" = "{
+ .clk_src = 4,
+ .clk_req = 4,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end #PCIE3 BH799BB
+ device ref pcie_rp6 off end # PCIE6 WWAN
+ device ref pcie_rp8 off end # PCIE8 SD card
+ device ref pcie_rp9 off end # PCIE9-12 SSD
+ device ref gspi1 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+ register "wake" = "GPE0_DW2_15"
+ device spi 0 on end
+ end # FPMCU
+ end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C1 (DB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(3, 1)"
+ device ref tcss_usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C1 (DB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(3, 1)"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A0 (DB)""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device ref usb2_port9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A0 (DB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device ref usb3_port1 on end
+ end
+ end
+ end
+ end
+ end
end
diff --git a/src/mainboard/google/brya/variants/volmar/variant.c b/src/mainboard/google/brya/variants/volmar/variant.c
new file mode 100644
index 0000000000..fef03f2b3e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/volmar/variant.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+ config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S));
+}