diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-08-18 05:26:40 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-09-08 02:46:01 +0000 |
| commit | 79503ef515967ffceab7bd2a16a381e6a02c3d30 (patch) | |
| tree | 37d2c833f2f3f681fb4b3b42b88b3d6682ace0b0 | |
| parent | 1e889d8082bc16a51f7b7ebaa6313cf8fb152b70 (diff) | |
vc/intel/fsp2/alderlake_n: Drop unused header files
Change-Id: I870fa65ff05cf5907d62b3af1b2f9c4334b62603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77260
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5 files changed, 0 insertions, 7655 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FirmwareVersionInfoHob.h deleted file mode 100644 index 98a16d7752..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,68 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR> - - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include <Uefi/UefiMultiPhase.h> -#include <Pi/PiBootMode.h> -#include <Pi/PiHob.h> - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h deleted file mode 100644 index ff33917f68..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h deleted file mode 100644 index c33aebf6de..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h +++ /dev/null @@ -1,3244 +0,0 @@ -/** @file - -Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - - -#include <MemInfoHob.h> - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x004A - Enable above 4GB MMIO resource support - Enable/disable above 4GB MMIO resource support - $EN_DIS -**/ - UINT8 EnableAbove4GBMmio; - -/** Offset 0x004B - Enable/Disable CrashLog Device 10 - Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog - $EN_DIS -**/ - UINT8 CpuCrashLogDevice; - -/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr000; - -/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr001; - -/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr010; - -/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr011; - -/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr020; - -/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr021; - -/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr030; - -/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr031; - -/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr100; - -/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr101; - -/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr110; - -/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr111; - -/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr120; - -/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr121; - -/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr130; - -/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr131; - -/** Offset 0x008C - RcompResistor settings - Indicates RcompResistor settings: Board-dependent -**/ - UINT16 RcompResistor; - -/** Offset 0x008E - RcompTarget settings - RcompTarget settings: board-dependent -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramMc0Ch0[2]; - -/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramMc0Ch1[2]; - -/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 - Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent -**/ - UINT8 DqsMapCpu2DramMc0Ch2[2]; - -/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 - Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqsMapCpu2DramMc0Ch3[2]; - -/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch0[2]; - -/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch1[2]; - -/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 - Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch2[2]; - -/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 - Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch3[2]; - -/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 - Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqMapCpu2DramMc0Ch0[16]; - -/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 - Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqMapCpu2DramMc0Ch1[16]; - -/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 - Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet -**/ - UINT8 DqMapCpu2DramMc0Ch2[16]; - -/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 - Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqMapCpu2DramMc0Ch3[16]; - -/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 - Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch0[16]; - -/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 - Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch1[16]; - -/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 - Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch2[16]; - -/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 - Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch3[16]; - -/** Offset 0x0128 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0129 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x012A - Ibecc - Enable/Disable Ibecc - $EN_DIS -**/ - UINT8 Ibecc; - -/** Offset 0x012B - IbeccOperationMode - In-Band ECC Operation Mode - 0:Protect base on address range, 1:Non-protected, 2:All protected -**/ - UINT8 IbeccOperationMode; - -/** Offset 0x012C - IbeccProtectedRangeEnable - In-Band ECC Protected Region Enable - $EN_DIS -**/ - UINT8 IbeccProtectedRangeEnable[8]; - -/** Offset 0x0134 - IbeccProtectedRangeBase - IBECC Protected Region Base -**/ - UINT32 IbeccProtectedRangeBase[8]; - -/** Offset 0x0154 - IbeccProtectedRangeMask - IBECC Protected Region Mask -**/ - UINT32 IbeccProtectedRangeMask[8]; - -/** Offset 0x0174 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0175 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0176 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0177 - Reserved -**/ - UINT8 Reserved0; - -/** Offset 0x0178 - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x017C - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x017E - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x017F - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x0180 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[16]; - -/** Offset 0x0190 - Platform Debug Consent - Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks - s0ix\n - \n - Enabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by - default, s0ix is viable\n - \n - Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users - 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x0191 - DCI Enable - Determine if to enable DCI debug from host - $EN_DIS -**/ - UINT8 DciEn; - -/** Offset 0x0192 - DCI DbC Mode - Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: - Set both USB2/3DBCEN; No Change: Comply with HW value - 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change -**/ - UINT8 DciDbcMode; - -/** Offset 0x0193 - Enable DCI ModPHY Power Gate - DEPRECATED - $EN_DIS -**/ - UINT8 DciModphyPg; - -/** Offset 0x0194 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x0195 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x0196 - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x0197 - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x0198 - HD Audio DMIC Link Clock Select - Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB - 0: Both, 1: ClkA, 2: ClkB -**/ - UINT8 PchHdaAudioLinkDmicClockSelect[2]; - -/** Offset 0x019A - Reserved -**/ - UINT8 Reserved1[5]; - -/** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x01A0 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 DmaControlGuarantee; - -/** Offset 0x01A1 - Reserved -**/ - UINT8 Reserved2[3]; - -/** Offset 0x01A4 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[9]; - -/** Offset 0x01C8 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x01C9 - Vtd Programming for Igd - 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar - programming disabled) - $EN_DIS -**/ - UINT8 VtdIgdEnable; - -/** Offset 0x01CA - Vtd Programming for Ipu - 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar - programming disabled) - $EN_DIS -**/ - UINT8 VtdIpuEnable; - -/** Offset 0x01CB - Vtd Programming for Iop - 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar - programming disabled) - $EN_DIS -**/ - UINT8 VtdIopEnable; - -/** Offset 0x01CC - Vtd Programming for ITbt - DEPRECATED - $EN_DIS -**/ - UINT8 VtdItbtEnable; - -/** Offset 0x01CD - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, - 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, - 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x01CE - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x01CF - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x01D0 - Board Type - MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, - 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server - 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, - 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x01D1 - Reserved -**/ - UINT8 Reserved3; - -/** Offset 0x01D2 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, - 2133, 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x01D4 - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at four different frequencies. - 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x01D5 - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x01D6 - DDR Speed Control - DDR Frequency and Gear control for all SAGV points. - 0:Auto, 1:Manual -**/ - UINT8 DdrSpeedControl; - -/** Offset 0x01D7 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x01D8 - Controller 0 Channel 0 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 0 - $EN_DIS -**/ - UINT8 DisableMc0Ch0; - -/** Offset 0x01D9 - Controller 0 Channel 1 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 1 - $EN_DIS -**/ - UINT8 DisableMc0Ch1; - -/** Offset 0x01DA - Controller 0 Channel 2 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 2 - $EN_DIS -**/ - UINT8 DisableMc0Ch2; - -/** Offset 0x01DB - Controller 0 Channel 3 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 3 - $EN_DIS -**/ - UINT8 DisableMc0Ch3; - -/** Offset 0x01DC - Controller 1 Channel 0 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 0 - $EN_DIS -**/ - UINT8 DisableMc1Ch0; - -/** Offset 0x01DD - Controller 1 Channel 1 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 1 - $EN_DIS -**/ - UINT8 DisableMc1Ch1; - -/** Offset 0x01DE - Controller 1 Channel 2 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 2 - $EN_DIS -**/ - UINT8 DisableMc1Ch2; - -/** Offset 0x01DF - Controller 1 Channel 3 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 3 - $EN_DIS -**/ - UINT8 DisableMc1Ch3; - -/** Offset 0x01E0 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x01E1 - SPD Profile Selected - Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, - 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP - User Profile 5 - 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP - Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x01E2 - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x01E3 - Reserved -**/ - UINT8 Reserved4; - -/** Offset 0x01E4 - Memory Voltage - DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM - chips) in millivolts from 0 - default to 1435mv. -**/ - UINT16 VddVoltage; - -/** Offset 0x01E6 - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x01E7 - tCL - CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT8 tCL; - -/** Offset 0x01E8 - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT8 tCWL; - -/** Offset 0x01E9 - Reserved -**/ - UINT8 Reserved5; - -/** Offset 0x01EA - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT16 tFAW; - -/** Offset 0x01EC - tRAS - RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT16 tRAS; - -/** Offset 0x01EE - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used - if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). -**/ - UINT8 tRCDtRP; - -/** Offset 0x01EF - Reserved -**/ - UINT8 Reserved6; - -/** Offset 0x01F0 - tREFI - Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT16 tREFI; - -/** Offset 0x01F2 - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT16 tRFC; - -/** Offset 0x01F4 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT8 tRRD; - -/** Offset 0x01F5 - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT8 tRTP; - -/** Offset 0x01F6 - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x01F7 - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT8 tWTR; - -/** Offset 0x01F8 - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x01F9 - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x01FA - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x01FB - CPU Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x01FC - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x01FD - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x01FE - SAGV Gear Ratio - Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 -**/ - UINT8 SaGvGear[4]; - -/** Offset 0x0202 - SAGV Frequency - SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. -**/ - UINT16 SaGvFreq[4]; - -/** Offset 0x020A - SAGV Disabled Gear Ratio - Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 -**/ - UINT8 GearRatio; - -/** Offset 0x020B - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x020C - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x0210 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x0214 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x0218 - HG dGPU Power Delay - HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 HgDelayAfterPwrEn; - -/** Offset 0x021A - HG dGPU Reset Delay - HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 HgDelayAfterHoldReset; - -/** Offset 0x021C - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x021E - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x021F - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0220 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0221 - Reserved -**/ - UINT8 Reserved7[3]; - -/** Offset 0x0224 - Temporary MMIO address for GMADR - Obsolete field now and it has been extended to 64 bit address, used GmAdr64 -**/ - UINT32 GmAdr; - -/** Offset 0x0228 - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x022C - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x022E - Hybrid Graphics GPIO information for PEG 0 - Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 CpuPcie0Rtd3Gpio[24]; - -/** Offset 0x0246 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x0247 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x0248 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x0249 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x024A - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x024C - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x024E - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x0250 - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x0252 - PCIe root port Function number for Hybrid Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x0253 - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x0254 - iTBT PCIe Multiple Segment setting - DEPRECATED - $EN_DIS -**/ - UINT8 PcieMultipleSegmentEnabled; - -/** Offset 0x0255 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x0256 - Lane Used of CSI port - Lane Used of each CSI port - 1:x1, 2:x2, 3:x3, 4:x4, 8:x8 -**/ - UINT8 IpuLaneUsed[8]; - -/** Offset 0x025E - Lane Used of CSI port - Speed of each CSI port - 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps -**/ - UINT8 CsiSpeed[8]; - -/** Offset 0x0266 - IMGU CLKOUT Configuration - The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. - $EN_DIS -**/ - UINT8 ImguClkOutEn[6]; - -/** Offset 0x026C - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 CpuPcieRpEnableMask; - -/** Offset 0x0270 - Assertion on Link Down GPIOs - GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down - GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs - 0:Disable, 1:Enable -**/ - UINT8 CpuPcieRpLinkDownGpios; - -/** Offset 0x0271 - Enable ClockReq Messaging - ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): - Enable ClockReq Messaging - 0:Disable, 1:Enable -**/ - UINT8 CpuPcieRpClockReqMsgEnable[3]; - -/** Offset 0x0274 - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; - 4: Gen4 (see: CPU_PCIE_SPEED). -**/ - UINT8 CpuPcieRpPcieSpeed[4]; - -/** Offset 0x0278 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x0279 - Program GPIOs for LFP on DDI port-A device - 0=Disabled,1(Default)=eDP, 2=MIPI DSI - 0:Disabled, 1:eDP, 2:MIPI DSI -**/ - UINT8 DdiPortAConfig; - -/** Offset 0x027A - Program GPIOs for LFP on DDI port-B device - 0(Default)=Disabled,1=eDP, 2=MIPI DSI - 0:Disabled, 1:eDP, 2:MIPI DSI -**/ - UINT8 DdiPortBConfig; - -/** Offset 0x027B - Enable or disable HPD of DDI port A - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortAHpd; - -/** Offset 0x027C - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x027D - Enable or disable HPD of DDI port C - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x027E - Enable or disable HPD of DDI port 1 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort1Hpd; - -/** Offset 0x027F - Enable or disable HPD of DDI port 2 - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPort2Hpd; - -/** Offset 0x0280 - Enable or disable HPD of DDI port 3 - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPort3Hpd; - -/** Offset 0x0281 - Enable or disable HPD of DDI port 4 - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPort4Hpd; - -/** Offset 0x0282 - Enable or disable DDC of DDI port A - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortADdc; - -/** Offset 0x0283 - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x0284 - Enable or disable DDC of DDI port C - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x0285 - Enable DDC setting of DDI Port 1 - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPort1Ddc; - -/** Offset 0x0286 - Enable DDC setting of DDI Port 2 - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPort2Ddc; - -/** Offset 0x0287 - Enable DDC setting of DDI Port 3 - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPort3Ddc; - -/** Offset 0x0288 - Enable DDC setting of DDI Port 4 - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPort4Ddc; - -/** Offset 0x0289 - Reserved -**/ - UINT8 Reserved8[7]; - -/** Offset 0x0290 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB) -**/ - UINT64 GmAdr64; - -/** Offset 0x0298 - Per-core HT Disable - Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, - 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value - of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have - HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. -**/ - UINT16 PerCoreHtDisable; - -/** Offset 0x029A - SA/Uncore voltage mode - SA/Uncore voltage mode; <b>0: Adaptive</b>; 1: Override. - $EN_DIS -**/ - UINT8 SaVoltageMode; - -/** Offset 0x029B - Reserved -**/ - UINT8 Reserved9; - -/** Offset 0x029C - SA/Uncore Voltage Override - The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override - mode. Valid Range 0 to 2000 -**/ - UINT16 SaVoltageOverride; - -/** Offset 0x029E - SA/Uncore Extra Turbo voltage - Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode. - Valid Range 0 to 2000 -**/ - UINT16 SaExtraTurboVoltage; - -/** Offset 0x02A0 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x02A1 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x02A2 - Reserved -**/ - UINT8 Reserved10[111]; - -/** Offset 0x0311 - Enable Gt CLOS - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 GtClosEnable; - -/** Offset 0x0312 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0313 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x0314 - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x0315 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x0316 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0317 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x031F - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0327 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x032F - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0333 - DMI ASPM Configuration:{Combo - Set ASPM Configuration - 0:Disabled, 1:L0s, 2:L1, 3:L1L0s -**/ - UINT8 DmiAspm; - -/** Offset 0x0334 - Enable/Disable DMI GEN3 Hardware Eq - Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0)(Default): Disable Hardware Eq, - Enabled(0x1): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiHweq; - -/** Offset 0x0335 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass - CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): - Enable Phase 23 Bypass - $EN_DIS -**/ - UINT8 Gen3EqPhase23Bypass; - -/** Offset 0x0336 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass - CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): - Enable Phase 3 Bypass - $EN_DIS -**/ - UINT8 Gen3EqPhase3Bypass; - -/** Offset 0x0337 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable - Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): - Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter - Coefficient Override - $EN_DIS -**/ - UINT8 Gen3LtcoEnable; - -/** Offset 0x0338 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable - Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): - Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote - Transmitter Coefficient/Preset Override - $EN_DIS -**/ - UINT8 Gen3RtcoRtpoEnable; - -/** Offset 0x0339 - DMI Gen3 Transmitter Pre-Cursor Coefficient - Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, - 2 is default for each lane -**/ - UINT8 DmiGen3Ltcpre[8]; - -/** Offset 0x0341 - DMI Gen3 Transmitter Post-Cursor Coefficient - Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default - for each lane -**/ - UINT8 DmiGen3Ltcpo[8]; - -/** Offset 0x0349 - PCIE Hw Eq Gen3 CoeffList Cm - CPU_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 CpuDmiHwEqGen3CoeffListCm[8]; - -/** Offset 0x0351 - PCIE Hw Eq Gen3 CoeffList Cp - CPU_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 CpuDmiHwEqGen3CoeffListCp[8]; - -/** Offset 0x0359 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable - Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, - Manual(0x1): Enable DmiGen3DsPresetEnable - $EN_DIS -**/ - UINT8 DmiGen3DsPresetEnable; - -/** Offset 0x035A - DMI Gen3 Root port preset Rx values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default - for each lane -**/ - UINT8 DmiGen3DsPortRxPreset[8]; - -/** Offset 0x0362 - DMI Gen3 Root port preset Tx values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default - for each lane -**/ - UINT8 DmiGen3DsPortTxPreset[8]; - -/** Offset 0x036A - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable - Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, - Manual(0x1): Enable DmiGen3UsPresetEnable - $EN_DIS -**/ - UINT8 DmiGen3UsPresetEnable; - -/** Offset 0x036B - DMI Gen3 Root port preset Rx values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default - for each lane -**/ - UINT8 DmiGen3UsPortRxPreset[8]; - -/** Offset 0x0373 - DMI Gen3 Root port preset Tx values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default - for each lane -**/ - UINT8 DmiGen3UsPortTxPreset[8]; - -/** Offset 0x037B - Reserved -**/ - UINT8 Reserved11[54]; - -/** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo - Set ASPM Control configuration - 0:Disabled, 1:L0s, 2:L1, 3:L1L0s -**/ - UINT8 DmiAspmCtrl; - -/** Offset 0x03B2 - DMI ASPM L1 exit Latency - Range: 0-7, 4 is default L1 exit Latency -**/ - UINT8 DmiAspmL1ExitLatency; - -/** Offset 0x03B3 - BIST on Reset - Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x03B4 - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x03B5 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x03B6 - Over clocking support - Over clocking support; <b>0: Disable</b>; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x03B7 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x03B8 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x03B9 - Core voltage mode - Core voltage mode; <b>0: Adaptive</b>; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x03BA - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x03BB - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x03BC - Enable or Disable CPU Ratio Override - Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 CpuRatioOverride; - -/** Offset 0x03BD - CPU ratio value - CPU ratio value. Valid Range 0 to 63 -**/ - UINT8 CpuRatio; - -/** Offset 0x03BE - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance. - 1: Maximum non-turbo performance. <b>2: Turbo performance </b> - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x03BF - Number of active big cores - Number of active big cores(Depends on Number of big cores). Default 0xFF means to - active all system supported big cores. <b>0xFF: Active all big cores</b>; 0: Disable - all big cores; 1: 1; 2: 2; 3: 3; - 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x03C0 - Processor Early Power On Configuration FCLK setting - <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x03C1 - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. <b>0: False</b>; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x03C2 - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x03C3 - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x03C4 - AVX3 Ratio Offset - DEPRECATED -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x03C5 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0: - Disable;<b> 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x03C6 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x03C8 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x03CA - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x03CC - Core PLL voltage offset - Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x03CD - Reserved -**/ - UINT8 Reserved12; - -/** Offset 0x03CE - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; <b>1: Enable.</b> - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x03CF - Ring voltage mode - Ring voltage mode; <b>0: Adaptive</b>; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x03D0 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x03D1 - Reserved -**/ - UINT8 Reserved13; - -/** Offset 0x03D2 - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x03D4 - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x03D6 - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x03D8 - Enable or Disable TME - Enable or Disable TME; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 TmeEnable; - -/** Offset 0x03D9 - Enable CPU CrashLog - Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 CpuCrashLogEnable; - -/** Offset 0x03DA - CPU Run Control - Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2: - No Change</b> - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x03DB - CPU Run Control Lock - Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x03DC - Reserved -**/ - UINT8 Reserved14[24]; - -/** Offset 0x03F4 - Core VF Point Offset Mode - Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. - In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, - setting a selected VF point; <b>0: Legacy</b>; 1: Selection. - 0:Legacy, 1:Selection -**/ - UINT8 CoreVfPointOffsetMode; - -/** Offset 0x03F5 - Reserved -**/ - UINT8 Reserved15; - -/** Offset 0x03F6 - Core VF Point Offset - Array used to specifies the Core Voltage Offset applied to the each selected VF - Point. This voltage is specified in millivolts. -**/ - UINT16 CoreVfPointOffset[15]; - -/** Offset 0x0414 - Core VF Point Offset Prefix - Sets the CoreVfPointOffset value as positive or negative for corresponding core - VF Point; <b>0: Positive </b>; 1: Negative. - 0:Positive, 1:Negative -**/ - UINT8 CoreVfPointOffsetPrefix[15]; - -/** Offset 0x0423 - Core VF Point Ratio - Array for the each selected Core VF Point to display the ration. -**/ - UINT8 CoreVfPointRatio[15]; - -/** Offset 0x0432 - Core VF Point Count - Number of supported Core Voltage & Frequency Point Offset -**/ - UINT8 CoreVfPointCount; - -/** Offset 0x0433 - Reserved -**/ - UINT8 Reserved16[25]; - -/** Offset 0x044C - Per Core Max Ratio override - Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new - favored core ratio to each Core. <b>0: Disable</b>, 1: enable - $EN_DIS -**/ - UINT8 PerCoreRatioOverride; - -/** Offset 0x044D - Per Core Current Max Ratio - Array for the Per Core Max Ratio -**/ - UINT8 PerCoreRatio[8]; - -/** Offset 0x0455 - Reserved -**/ - UINT8 Reserved17[5]; - -/** Offset 0x045A - Pvd Ratio Threshold - Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default. -**/ - UINT8 PvdRatioThreshold; - -/** Offset 0x045B - Support Unlimited ICCMAX - DEPRECATED - $EN_DIS -**/ - UINT8 UnlimitedIccMax; - -/** Offset 0x045C - Enable CPU CrashLog GPRs dump - Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only - disable Smm GPRs dump - 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled -**/ - UINT8 CrashLogGprs; - -/** Offset 0x045D - Reserved -**/ - UINT8 Reserved18[62]; - -/** Offset 0x049B - BCLK Frequency Source - Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK - 1:CPU BCLK, 2:PCH BCLK, 3:External CLK -**/ - UINT8 BclkSource; - -/** Offset 0x049C - GPIO Override - Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings - before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO - configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use -**/ - UINT8 GpioOverride; - -/** Offset 0x049D - Reserved -**/ - UINT8 Reserved19[3]; - -/** Offset 0x04A0 - CPU BCLK OC Frequency - CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 - - Auto</b>. Range is 8000-50000 (10KHz). -**/ - UINT32 CpuBclkOcFrequency; - -/** Offset 0x04A4 - Reserved -**/ - UINT8 Reserved20[40]; - -/** Offset 0x04CC - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x04CD -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x04CE - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x04CF - Reserved -**/ - UINT8 Reserved21; - -/** Offset 0x04D0 - PrmrrSize - Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable -**/ - UINT32 PrmrrSize; - -/** Offset 0x04D4 - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x04D8 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x04E0 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x04E4 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x04E8 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x04EC - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x04F0 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x04F4 - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x04F8 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0500 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0508 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0509 - Reserved -**/ - UINT8 Reserved22[32]; - -/** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[28]; - -/** Offset 0x0545 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[28]; - -/** Offset 0x0561 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; - -/** Offset 0x057D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; - -/** Offset 0x0599 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; - -/** Offset 0x05B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; - -/** Offset 0x05D1 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; - -/** Offset 0x05ED - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; - -/** Offset 0x0609 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; - -/** Offset 0x0625 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[28]; - -/** Offset 0x0641 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; - -/** Offset 0x065D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; - -/** Offset 0x0679 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; - -/** Offset 0x0695 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; - -/** Offset 0x06B1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x06B9 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x06C1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x06C9 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x06D1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x06D9 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x06E1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x06E9 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x06F1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x06F9 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x0701 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0709 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0711 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0719 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0721 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0729 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0731 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0739 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0741 - PCH LPC Enhanced Port 80 Decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0742 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - 0:LPC, 1:PCI -**/ - UINT8 PchPort80Route; - -/** Offset 0x0743 - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x0744 - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x0745 - Reserved -**/ - UINT8 Reserved23; - -/** Offset 0x0746 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x0748 - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x0749 - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[18]; - -/** Offset 0x075B - Reserved -**/ - UINT8 Reserved24[14]; - -/** Offset 0x0769 - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[18]; - -/** Offset 0x077B - Reserved -**/ - UINT8 Reserved25[93]; - -/** Offset 0x07D8 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x07DC - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x07DD - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x07DE - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHdaEnable; - -/** Offset 0x07DF - Enable HDA SDI lanes - Enable/disable HDA SDI lanes. -**/ - UINT8 PchHdaSdiEnable[2]; - -/** Offset 0x07E1 - HDA Power/Clock Gating (PGD/CGD) - Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: - FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 PchHdaTestPowerClockGating; - -/** Offset 0x07E2 - Enable HD Audio DMIC_N Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. -**/ - UINT8 PchHdaAudioLinkDmicEnable[2]; - -/** Offset 0x07E4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) - Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* -**/ - UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; - -/** Offset 0x07EC - DMIC<N> ClkB Pin Muxing - Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* -**/ - UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; - -/** Offset 0x07F4 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x07F5 - Reserved -**/ - UINT8 Reserved26[3]; - -/** Offset 0x07F8 - DMIC<N> Data Pin Muxing - Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* -**/ - UINT32 PchHdaAudioLinkDmicDataPinMux[2]; - -/** Offset 0x0800 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 -**/ - UINT8 PchHdaAudioLinkSspEnable[6]; - -/** Offset 0x0806 - Enable HD Audio SoundWire#N Link - Enable/disable HD Audio SNDW#N link. Muxed with HDA. -**/ - UINT8 PchHdaAudioLinkSndwEnable[4]; - -/** Offset 0x080A - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x080B - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T - 0: 2T, 2: 4T, 3: 8T, 4: 16T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x080C - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x080D - CNVi DDR RFI Mitigation - Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviDdrRfim; - -/** Offset 0x080E - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x080F - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x0810 - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x0811 - Reserved -**/ - UINT8 Reserved27[3]; - -/** Offset 0x0814 - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x0818 - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x0819 - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x081A - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x081B - Reserved -**/ - UINT8 Reserved28; - -/** Offset 0x081C - Serial Io Uart Debug Mmio Base - Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode - = SerialIoUartPci. -**/ - UINT32 SerialIoUartDebugMmioBase; - -/** Offset 0x0820 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0821 - GT PLL voltage offset - Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0822 - Ring PLL voltage offset - Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x0823 - System Agent PLL voltage offset - Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x0824 - Memory Controller PLL voltage offset - Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x0825 - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable - Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie0En; - -/** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable - Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie1En; - -/** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable - Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie2En; - -/** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable - Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie3En; - -/** Offset 0x082A - TCSS USB HOST (xHCI) Enable - Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below - $EN_DIS -**/ - UINT8 TcssXhciEn; - -/** Offset 0x082B - TCSS USB DEVICE (xDCI) Enable - Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled - $EN_DIS -**/ - UINT8 TcssXdciEn; - -/** Offset 0x082C - TCSS DMA0 Enable - Set TCSS DMA0. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssDma0En; - -/** Offset 0x082D - TCSS DMA1 Enable - Set TCSS DMA1. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssDma1En; - -/** Offset 0x082E - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x082F - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x0830 - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x0831 - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x0832 - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x0833 - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x0834 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x0835 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0836 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0837 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0838 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0839 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x083A - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x083B - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x083C - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x083D - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x083E - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x083F - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x0840 - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x0841 - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x0842 - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x0843 - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x0844 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x0845 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0846 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0847 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0848 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0849 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x084A - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x084B - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x084C - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x084D - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x084E - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x084F - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x0850 - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x0851 - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x0852 - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x0853 - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x0854 - Reserved -**/ - UINT8 Reserved29; - -/** Offset 0x0855 - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x0856 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x0857 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x0858 - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x0859 - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x085A - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x085B - Reserved -**/ - UINT8 Reserved30; - -/** Offset 0x085C - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x085D - New Features 1 - MRC - New Feature Enabling 1, <b>0:Disable</b>, 1:Enable - 0:Disable, 1:Enable -**/ - UINT8 NewFeatureEnable1; - -/** Offset 0x085E - New Features 2 - MRC - New Feature Enabling 2, <b>0:Disable</b>, 1:Enable - 0:Disable, 1:Enable -**/ - UINT8 NewFeatureEnable2; - -/** Offset 0x085F - Duty Cycle Correction Training - Enable/Disable Duty Cycle Correction Training - $EN_DIS -**/ - UINT8 DCC; - -/** Offset 0x0860 - Read Voltage Centering 1D - Enable/Disable Read Voltage Centering 1D - $EN_DIS -**/ - UINT8 RDVC1D; - -/** Offset 0x0861 - TxDqTCO Comp Training - Enable/Disable TxDqTCO Comp Training - $EN_DIS -**/ - UINT8 TXTCO; - -/** Offset 0x0862 - ClkTCO Comp Training - Enable/Disable ClkTCO Comp Training - $EN_DIS -**/ - UINT8 CLKTCO; - -/** Offset 0x0863 - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x0864 - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x0865 - DIMM CA ODT Training - Enable/Disable DIMM CA ODT Training - $EN_DIS -**/ - UINT8 DIMMODTCA; - -/** Offset 0x0866 - TxDqsTCO Comp Training - Enable/Disable TxDqsTCO Comp Training - $EN_DIS -**/ - UINT8 TXTCODQS; - -/** Offset 0x0867 - CMD/CTL Drive Strength Up/Dn 2D - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D - $EN_DIS -**/ - UINT8 CMDDRUD; - -/** Offset 0x0868 - VccDLL Bypass Training - Enable/Disable VccDLL Bypass Training - $EN_DIS -**/ - UINT8 VCCDLLBP; - -/** Offset 0x0869 - PanicVttDnLp Training - Enable/Disable PanicVttDnLp Training - $EN_DIS -**/ - UINT8 PVTTDNLP; - -/** Offset 0x086A - Read Vref Decap Training* - Enable/Disable Read Vref Decap Training* - $EN_DIS -**/ - UINT8 RDVREFDC; - -/** Offset 0x086B - Vddq Training - Enable/Disable Vddq Training - $EN_DIS -**/ - UINT8 VDDQT; - -/** Offset 0x086C - Rank Margin Tool Per Bit - Enable/Disable Rank Margin Tool Per Bit - $EN_DIS -**/ - UINT8 RMTBIT; - -/** Offset 0x086D - Reserved -**/ - UINT8 Reserved31[2]; - -/** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x0870 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x0871 - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x0872 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6] Default is 0x30CC -**/ - UINT16 ChHashMask; - -/** Offset 0x0874 - Base reference clock value - Base reference clock value, in Hertz(Default is 100Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x0878 - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x087A - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x087C - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x087D - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x087E - Reserved -**/ - UINT8 Reserved32; - -/** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc0Ch0Dimm0; - -/** Offset 0x0880 - Idle Energy Mc0Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc0Ch0Dimm1; - -/** Offset 0x0881 - Idle Energy Mc0Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc0Ch1Dimm0; - -/** Offset 0x0882 - Idle Energy Mc0Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc0Ch1Dimm1; - -/** Offset 0x0883 - Idle Energy Mc1Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc1Ch0Dimm0; - -/** Offset 0x0884 - Idle Energy Mc1Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc1Ch0Dimm1; - -/** Offset 0x0885 - Idle Energy Mc1Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc1Ch1Dimm0; - -/** Offset 0x0886 - Idle Energy Mc1Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyMc1Ch1Dimm1; - -/** Offset 0x0887 - PowerDown Energy Mc0Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc0Ch0Dimm0; - -/** Offset 0x0888 - PowerDown Energy Mc0Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc0Ch0Dimm1; - -/** Offset 0x0889 - PowerDown Energy Mc0Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc0Ch1Dimm0; - -/** Offset 0x088A - PowerDown Energy Mc0Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc0Ch1Dimm1; - -/** Offset 0x088B - PowerDown Energy Mc1Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc1Ch0Dimm0; - -/** Offset 0x088C - PowerDown Energy Mc1Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc1Ch0Dimm1; - -/** Offset 0x088D - PowerDown Energy Mc1Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc1Ch1Dimm0; - -/** Offset 0x088E - PowerDown Energy Mc1Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) -**/ - UINT8 PdEnergyMc1Ch1Dimm1; - -/** Offset 0x088F - Activate Energy Mc0Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc0Ch0Dimm0; - -/** Offset 0x0890 - Activate Energy Mc0Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc0Ch0Dimm1; - -/** Offset 0x0891 - Activate Energy Mc0Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc0Ch1Dimm0; - -/** Offset 0x0892 - Activate Energy Mc0Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc0Ch1Dimm1; - -/** Offset 0x0893 - Activate Energy Mc1Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc1Ch0Dimm0; - -/** Offset 0x0894 - Activate Energy Mc1Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc1Ch0Dimm1; - -/** Offset 0x0895 - Activate Energy Mc1Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc1Ch1Dimm0; - -/** Offset 0x0896 - Activate Energy Mc1Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyMc1Ch1Dimm1; - -/** Offset 0x0897 - Read Energy Mc0Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc0Ch0Dimm0; - -/** Offset 0x0898 - Read Energy Mc0Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc0Ch0Dimm1; - -/** Offset 0x0899 - Read Energy Mc0Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc0Ch1Dimm0; - -/** Offset 0x089A - Read Energy Mc0Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc0Ch1Dimm1; - -/** Offset 0x089B - Read Energy Mc1Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc1Ch0Dimm0; - -/** Offset 0x089C - Read Energy Mc1Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc1Ch0Dimm1; - -/** Offset 0x089D - Read Energy Mc1Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc1Ch1Dimm0; - -/** Offset 0x089E - Read Energy Mc1Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyMc1Ch1Dimm1; - -/** Offset 0x089F - Write Energy Mc0Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc0Ch0Dimm0; - -/** Offset 0x08A0 - Write Energy Mc0Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc0Ch0Dimm1; - -/** Offset 0x08A1 - Write Energy Mc0Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc0Ch1Dimm0; - -/** Offset 0x08A2 - Write Energy Mc0Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc0Ch1Dimm1; - -/** Offset 0x08A3 - Write Energy Mc1Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc1Ch0Dimm0; - -/** Offset 0x08A4 - Write Energy Mc1Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc1Ch0Dimm1; - -/** Offset 0x08A5 - Write Energy Mc1Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc1Ch1Dimm0; - -/** Offset 0x08A6 - Write Energy Mc1Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyMc1Ch1Dimm1; - -/** Offset 0x08A7 - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Dfault is 0x00 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x08A8 - Reserved -**/ - UINT8 Reserved33[2]; - -/** Offset 0x08AA - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x08AB - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x08AC - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x08AD - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x08AE - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x08AF - Reserved -**/ - UINT8 Reserved34; - -/** Offset 0x08B0 - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x08B1 - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x08B2 - Power Down Mode - This option controls command bus tristating during idle periods - 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto -**/ - UINT8 PowerDownMode; - -/** Offset 0x08B3 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x08B4 - Page Close Idle Timeout - This option controls Page Close Idle Timeout - 0:Enabled, 1:Disabled -**/ - UINT8 DisPgCloseIdleTimeout; - -/** Offset 0x08B5 - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, - Rank0 is terminating and Rank1 is non-terminating</b> -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x08B6 - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x08B7 - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x08B8 - Ask MRC to clear memory content - Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x08B9 - LpDdrDqDqsReTraining - Enable/Disable TxDqDqs ReTraining for LP4/5 and DDR5 - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x08BA - TCSS USB Port Enable - Bitmap for per port enabling -**/ - UINT8 UsbTcPortEnPreMem; - -/** Offset 0x08BB - Reserved -**/ - UINT8 Reserved35; - -/** Offset 0x08BC - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x08BE - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x08BF - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x08C0 - WRC Feature - Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports - IO devices allocating onto the ring and into LLC. WRC is fused on by default. - $EN_DIS -**/ - UINT8 WrcFeatureEnable; - -/** Offset 0x08C1 - Reserved -**/ - UINT8 Reserved36[3]; - -/** Offset 0x08C4 - BCLK RFI Frequency - Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No - RFI Tuning</b>. Range is 98Mhz-100Mhz. -**/ - UINT32 BclkRfiFreq[4]; - -/** Offset 0x08D4 - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x08D6 - Enable PCIe IMR - 0: Disable(AUTO), 1: Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x08D7 - Enable PCIe IMR - 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select - the Root port location from PCH PCIe or SA PCIe - $EN_DIS -**/ - UINT8 PcieImrRpLocation; - -/** Offset 0x08D8 - Root port number for IMR. - Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port - from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 -**/ - UINT8 PcieImrRpSelection; - -/** Offset 0x08D9 - SerialDebugMrcLevel - MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 SerialDebugMrcLevel; - -/** Offset 0x08DA - Ddr4OneDpc - DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, - or on both (default) - 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled -**/ - UINT8 Ddr4OneDpc; - -/** Offset 0x08DB - Reserved -**/ - UINT8 Reserved37[3]; - -/** Offset 0x08DE - REFRESH_PANIC_WM - DEPRECATED -**/ - UINT8 RefreshPanicWm; - -/** Offset 0x08DF - REFRESH_HP_WM - DEPRECATED -**/ - UINT8 RefreshHpWm; - -/** Offset 0x08E0 - Command Pins Mapping - BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller - 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. -**/ - UINT8 Lp5CccConfig; - -/** Offset 0x08E1 - Command Pins Mirrored - BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller - 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. -**/ - UINT8 CmdMirror; - -/** Offset 0x08E2 - Reserved -**/ - UINT8 Reserved38[9]; - -/** Offset 0x08EB - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x08EC - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x08ED - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x08EE - Reserved -**/ - UINT8 Reserved39; - -/** Offset 0x08EF - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x08F0 - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x08F1 - Reserved -**/ - UINT8 Reserved40[3]; - -/** Offset 0x08F4 - PMR Size - Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot -**/ - UINT32 DmaBufferSize; - -/** Offset 0x08F8 - VT-d/IOMMU Boot Policy - BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS -**/ - UINT8 PreBootDmaMask; - -/** Offset 0x08F9 - Reserved -**/ - UINT8 Reserved41[95]; - -/** Offset 0x0958 - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x095A - BiosSize - The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != - 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected - Range) so that a BIOS Update Script can be stored in the DPR. -**/ - UINT16 BiosSize; - -/** Offset 0x095C - Reserved -**/ - UINT8 Reserved42[12]; - -/** Offset 0x0968 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x0969 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x096A - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x096B - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x096C - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x096D - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x096E - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x096F - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x0970 - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x0971 - Skip CPU replacement check - Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check - $EN_DIS -**/ - UINT8 SkipCpuReplacementCheck; - -/** Offset 0x0972 - Reserved -**/ - UINT8 Reserved43[2]; - -/** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 - Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT32 CpuPcie1Rtd3Gpio[24]; - -/** Offset 0x09D4 - Hybrid Graphics GPIO information for PEG 2 - Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT32 CpuPcie2Rtd3Gpio[24]; - -/** Offset 0x0A34 - Hybrid Graphics GPIO information for PEG 3 - Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT32 CpuPcie3Rtd3Gpio[24]; - -/** Offset 0x0A94 - Avx2 Voltage Guardband Scaling Factor - AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in - 1/100 units, where a value of 125 would apply a 1.25 scale factor. -**/ - UINT8 Avx2VoltageScaleFactor; - -/** Offset 0x0A95 - Avx512 Voltage Guardband Scaling Factor - DEPRECATED -**/ - UINT8 Avx512VoltageScaleFactor; - -/** Offset 0x0A96 - Serial Io Uart Debug Mode - Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartDebugMode; - -/** Offset 0x0A97 - Reserved -**/ - UINT8 Reserved44; - -/** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT - Select RX pin muxing for SerialIo UART used for debug -**/ - UINT32 SerialIoUartDebugRxPinMux; - -/** Offset 0x0A9C - SerialIoUartDebugTxPinMux - FSPM - Select TX pin muxing for SerialIo UART used for debug -**/ - UINT32 SerialIoUartDebugTxPinMux; - -/** Offset 0x0AA0 - SerialIoUartDebugRtsPinMux - FSPM - Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. -**/ - UINT32 SerialIoUartDebugRtsPinMux; - -/** Offset 0x0AA4 - SerialIoUartDebugCtsPinMux - FSPM - Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. -**/ - UINT32 SerialIoUartDebugCtsPinMux; - -/** Offset 0x0AA8 - Reserved -**/ - UINT8 Reserved45[130]; - -/** Offset 0x0B2A - LP5 Bank Mode - LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0 - 0:Auto, 1:8 Bank Mode, 2:16 Bank Mode, 3:BG Mode -**/ - UINT8 Lp5BankMode; - -/** Offset 0x0B2B - Reserved -**/ - UINT8 Reserved46[13]; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0B38 -**/ - UINT8 UnusedUpdSpace33[6]; - -/** Offset 0x0B3E -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h deleted file mode 100644 index 02b544a04e..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h +++ /dev/null @@ -1,3975 +0,0 @@ -/** @file - -Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0044 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0048 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x004C - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x0050 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x0054 - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x0055 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x0056 - Reserved -**/ - UINT8 Reserved0[2]; - -/** Offset 0x0058 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x005C - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0060 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0061 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0062 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x006A - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x0072 - Reserved -**/ - UINT8 Reserved1[34]; - -/** Offset 0x0094 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x00A4 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x00AE - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x00AF - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x00B4 - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x00B5 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x00BD - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x00BE - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x00BF - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x00C0 - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x00C1 - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x00C2 - Reserved -**/ - UINT8 Reserved3[2]; - -/** Offset 0x00C4 - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x00C8 - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x00C9 - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x00CA - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x00CB - SPIn Device Mode - Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available - modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden -**/ - UINT8 SerialIoSpiMode[7]; - -/** Offset 0x00D2 - SPI<N> Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, - 1:SerialIoSpiCsActiveHigh -**/ - UINT8 SerialIoSpiCsPolarity[14]; - -/** Offset 0x00E0 - SPI<N> Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpiCsEnable[14]; - -/** Offset 0x00EE - SPIn Default Chip Select Output - Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available - options: 0:CS0, 1:CS1 -**/ - UINT8 SerialIoSpiDefaultCsOutput[7]; - -/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW - Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, - SPI1, ... Available options: 0:HW, 1:SW -**/ - UINT8 SerialIoSpiCsMode[7]; - -/** Offset 0x00FC - SPIn Default Chip Select State Low/High - Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... - Available options: 0:Low, 1:High -**/ - UINT8 SerialIoSpiCsState[7]; - -/** Offset 0x0103 - UARTn Device Mode - Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available - modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartMode[7]; - -/** Offset 0x010A - Reserved -**/ - UINT8 Reserved4[2]; - -/** Offset 0x010C - Default BaudRate for each Serial IO UART - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 SerialIoUartBaudRate[7]; - -/** Offset 0x0128 - Default ParityType for each Serial IO UART - Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartParity[7]; - -/** Offset 0x012F - Default DataBits for each Serial IO UART - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 SerialIoUartDataBits[7]; - -/** Offset 0x0136 - Default StopBits for each Serial IO UART - Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: - TwoStopBits -**/ - UINT8 SerialIoUartStopBits[7]; - -/** Offset 0x013D - Power Gating mode for each Serial IO UART that works in COM mode - Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto -**/ - UINT8 SerialIoUartPowerGating[7]; - -/** Offset 0x0144 - Enable Dma for each Serial IO UART that supports it - Set DMA/PIO mode. 0: Disabled, 1: Enabled -**/ - UINT8 SerialIoUartDmaEnable[7]; - -/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS lines. -**/ - UINT8 SerialIoUartAutoFlow[7]; - -/** Offset 0x0152 - Reserved -**/ - UINT8 Reserved5[2]; - -/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy - Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. -**/ - UINT32 SerialIoUartRtsPinMuxPolicy[7]; - -/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy - Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. -**/ - UINT32 SerialIoUartCtsPinMuxPolicy[7]; - -/** Offset 0x018C - SerialIoUartRxPinMuxPolicy - Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for - possible values. -**/ - UINT32 SerialIoUartRxPinMuxPolicy[7]; - -/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy - Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for - possible values. -**/ - UINT32 SerialIoUartTxPinMuxPolicy[7]; - -/** Offset 0x01C4 - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, - 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used - for debug purpose. - 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x01C5 - Serial IO UART DBG2 table - Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b> - 1: Enable. -**/ - UINT8 SerialIoUartDbg2[7]; - -/** Offset 0x01CC - I2Cn Device Mode - Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available - modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden -**/ - UINT8 SerialIoI2cMode[8]; - -/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing - Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for - possible values. -**/ - UINT32 PchSerialIoI2cSdaPinMux[8]; - -/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing - Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for - possible values. -**/ - UINT32 PchSerialIoI2cSclPinMux[8]; - -/** Offset 0x0214 - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination - respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[8]; - -/** Offset 0x021C - ISH GP GPIO Pin Muxing - Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER -**/ - UINT32 IshGpGpioPinMuxing[8]; - -/** Offset 0x023C - ISH UART Rx Pin Muxing - Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* -**/ - UINT32 IshUartRxPinMuxing[3]; - -/** Offset 0x0248 - ISH UART Tx Pin Muxing - Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* -**/ - UINT32 IshUartTxPinMuxing[3]; - -/** Offset 0x0254 - ISH UART Rts Pin Muxing - Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. -**/ - UINT32 IshUartRtsPinMuxing[3]; - -/** Offset 0x0260 - ISH UART Rts Pin Muxing - Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. -**/ - UINT32 IshUartCtsPinMuxing[3]; - -/** Offset 0x026C - ISH I2C SDA Pin Muxing - Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. -**/ - UINT32 IshI2cSdaPinMuxing[3]; - -/** Offset 0x0278 - ISH I2C SCL Pin Muxing - Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. -**/ - UINT32 IshI2cSclPinMuxing[3]; - -/** Offset 0x0284 - ISH SPI MOSI Pin Muxing - Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. -**/ - UINT32 IshSpiMosiPinMuxing[2]; - -/** Offset 0x028C - ISH SPI MISO Pin Muxing - Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. -**/ - UINT32 IshSpiMisoPinMuxing[2]; - -/** Offset 0x0294 - ISH SPI CLK Pin Muxing - Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. -**/ - UINT32 IshSpiClkPinMuxing[2]; - -/** Offset 0x029C - ISH SPI CS#N Pin Muxing - Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible - values. N-SPI number, 0-1. -**/ - UINT32 IshSpiCsPinMuxing[4]; - -/** Offset 0x02AC - ISH GP GPIO Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination - respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index - 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 -**/ - UINT8 IshGpGpioPadTermination[8]; - -/** Offset 0x02B4 - ISH UART Rx Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination - respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 - Rx, and so on. -**/ - UINT8 IshUartRxPadTermination[3]; - -/** Offset 0x02B7 - ISH UART Tx Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination - respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 - Tx, and so on. -**/ - UINT8 IshUartTxPadTermination[3]; - -/** Offset 0x02BA - ISH UART Rts Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination - respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 - Rts, and so on. -**/ - UINT8 IshUartRtsPadTermination[3]; - -/** Offset 0x02BD - ISH UART Rts Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination - respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 - Cts, and so on. -**/ - UINT8 IshUartCtsPadTermination[3]; - -/** Offset 0x02C0 - ISH I2C SDA Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination - respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, - and so on. -**/ - UINT8 IshI2cSdaPadTermination[3]; - -/** Offset 0x02C3 - ISH I2C SCL Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination - respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, - and so on. -**/ - UINT8 IshI2cSclPadTermination[3]; - -/** Offset 0x02C6 - ISH SPI MOSI Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination - respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 - Mosi, and so on. -**/ - UINT8 IshSpiMosiPadTermination[2]; - -/** Offset 0x02C8 - ISH SPI MISO Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination - respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 - Miso, and so on. -**/ - UINT8 IshSpiMisoPadTermination[2]; - -/** Offset 0x02CA - ISH SPI CLK Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination - respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, - and so on. -**/ - UINT8 IshSpiClkPadTermination[2]; - -/** Offset 0x02CC - ISH SPI CS#N Pad termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination - respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 - Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 -**/ - UINT8 IshSpiCsPadTermination[4]; - -/** Offset 0x02D0 - Enable PCH ISH SPI Cs#N pins assigned - Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs - number: 0-1 -**/ - UINT8 PchIshSpiCsEnable[4]; - -/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2PhyPetxiset[16]; - -/** Offset 0x02E4 - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2PhyTxiset[16]; - -/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2PhyPredeemp[16]; - -/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2PhyPehalfbit[16]; - -/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default - = 00h</b>. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x033C -**/ - UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; - -/** Offset 0x0346 -**/ - UINT8 PchUsb3HsioFilterSelNEnable[10]; - -/** Offset 0x0350 -**/ - UINT8 PchUsb3HsioFilterSelPEnable[10]; - -/** Offset 0x035A -**/ - UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; - -/** Offset 0x0364 -**/ - UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; - -/** Offset 0x036E -**/ - UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; - -/** Offset 0x0378 -**/ - UINT8 PchUsb3HsioFilterSelN[10]; - -/** Offset 0x0382 -**/ - UINT8 PchUsb3HsioFilterSelP[10]; - -/** Offset 0x038C - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x038D - Enable PCH TSN - Enable/disable TSN on the PCH. - $EN_DIS -**/ - UINT8 PchTsnEnable; - -/** Offset 0x038E - TSN Link Speed - Set TSN Link Speed. - 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps -**/ - UINT8 PchTsnLinkSpeed; - -/** Offset 0x038F - Reserved -**/ - UINT8 Reserved6[9]; - -/** Offset 0x0398 - PCIe PTM enable/disable - Enable/disable Precision Time Measurement for PCIE Root Ports. -**/ - UINT8 PciePtm[28]; - -/** Offset 0x03B4 - PCIe DPC enable/disable - Enable/disable Downstream Port Containment for PCIE Root Ports. -**/ - UINT8 PcieDpc[28]; - -/** Offset 0x03D0 - PCIe DPC extensions enable/disable - Enable/disable Downstream Port Containment Extensions for PCIE Root Ports. -**/ - UINT8 PcieEdpc[28]; - -/** Offset 0x03EC - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x03ED - Reserved -**/ - UINT8 Reserved7[3]; - -/** Offset 0x03F0 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounce; - -/** Offset 0x03F4 - PCH eSPI Host and Device BME enabled - PCH eSPI Host and Device BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x03F5 - PCH eSPI Link Configuration Lock (SBLCL) - Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves - addresseses from range 0x0 - 0x7FF - $EN_DIS -**/ - UINT8 PchEspiLockLinkConfiguration; - -/** Offset 0x03F6 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states - Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0 -**/ - UINT8 PchFivrExtV1p05RailEnabledStates; - -/** Offset 0x03F7 - Mask to enable the platform configuration of external V1p05 VR rail - External V1P05 Rail Supported Configuration -**/ - UINT8 PchFivrExtV1p05RailSupportedVoltageStates; - -/** Offset 0x03F8 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states - Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) -**/ - UINT16 PchFivrExtV1p05RailVoltage; - -/** Offset 0x03FA - External V1P05 Icc Max Value - Granularity of this setting is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtV1p05RailIccMax; - -/** Offset 0x03FB - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states - Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 -**/ - UINT8 PchFivrExtVnnRailEnabledStates; - -/** Offset 0x03FC - Mask to enable the platform configuration of external Vnn VR rail - External Vnn Rail Supported Configuration -**/ - UINT8 PchFivrExtVnnRailSupportedVoltageStates; - -/** Offset 0x03FD - Reserved -**/ - UINT8 Reserved8; - -/** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states - Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 -**/ - UINT16 PchFivrExtVnnRailVoltage; - -/** Offset 0x0400 - External Vnn Icc Max Value that will be used in S0ix/Sx states - Granularity of this setting is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtVnnRailIccMax; - -/** Offset 0x0401 - Mask to enable the usage of external Vnn VR rail in Sx states - Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in - Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0 -**/ - UINT8 PchFivrExtVnnRailSxEnabledStates; - -/** Offset 0x0402 - External Vnn Voltage Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments - (0=0mV, 1=2.5mV, 2=5mV...) -**/ - UINT16 PchFivrExtVnnRailSxVoltage; - -/** Offset 0x0404 - External Vnn Icc Max Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting - is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtVnnRailSxIccMax; - -/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to low current mode voltage. -**/ - UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; - -/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to retention mode voltage. -**/ - UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; - -/** Offset 0x0407 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to retention mode voltage. -**/ - UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; - -/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage - This field has 1us resolution. When value is 0 Transition to 0V is disabled. -**/ - UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; - -/** Offset 0x040A - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x040B - Reserved -**/ - UINT8 Reserved9; - -/** Offset 0x040C - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x0410 - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x0414 - FIVR Dynamic Power Management - Enable/Disable FIVR Dynamic Power Management. - $EN_DIS -**/ - UINT8 PchFivrDynPm; - -/** Offset 0x0415 - FIVR VCCST ICCMax Control - Enable/Disable FIVR VCCST ICCMax Control. - $EN_DIS -**/ - UINT8 PchFivrVccstIccMaxControl; - -/** Offset 0x0416 - External V1P05 Icc Max Value - Granularity of this setting is 1mA and maximal possible value is 500mA -**/ - UINT16 PchFivrExtV1p05RailIccMaximum; - -/** Offset 0x0418 - External Vnn Icc Max Value that will be used in S0ix/Sx states - Granularity of this setting is 1mA and maximal possible value is 500mA -**/ - UINT16 PchFivrExtVnnRailIccMaximum; - -/** Offset 0x041A - External Vnn Icc Max Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting - is 1mA and maximal possible value is 500mA -**/ - UINT16 PchFivrExtVnnRailSxIccMaximum; - -/** Offset 0x041C - Extented BIOS Direct Read Decode enable - Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. - 0: disabled (default), 1: enabled - $EN_DIS -**/ - UINT8 PchSpiExtendedBiosDecodeRangeEnable; - -/** Offset 0x041D - Reserved -**/ - UINT8 Reserved10[3]; - -/** Offset 0x0420 - Extended BIOS Direct Read Decode Range base - Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. -**/ - UINT32 PchSpiExtendedBiosDecodeRangeBase; - -/** Offset 0x0424 - Extended BIOS Direct Read Decode Range limit - Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. -**/ - UINT32 PchSpiExtendedBiosDecodeRangeLimit; - -/** Offset 0x0428 - Reserved -**/ - UINT8 Reserved11[12]; - -/** Offset 0x0434 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 CnviMode; - -/** Offset 0x0435 - Reserved -**/ - UINT8 Reserved12; - -/** Offset 0x0436 - CNVi BT Core - Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtCore; - -/** Offset 0x0437 - CNVi BT Audio Offload - Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtAudioOffload; - -/** Offset 0x0438 - CNVi RF_RESET pin muxing - Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) - or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. -**/ - UINT32 CnviRfResetPinMux; - -/** Offset 0x043C - CNVi CLKREQ pin muxing - Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) - or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* - in GpioPins*.h. -**/ - UINT32 CnviClkreqPinMux; - -/** Offset 0x0440 - Enable Host C10 reporting through eSPI - Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. - $EN_DIS -**/ - UINT8 PchEspiHostC10ReportEnable; - -/** Offset 0x0441 - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PmcUsb2PhySusPgEnable; - -/** Offset 0x0442 - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x0443 - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x0444 - External V1P05 Control Ramp Timer value - Hold off time to be used when changing the v1p05_ctrl for external bypass value in us -**/ - UINT8 PchFivrExtV1p05RailCtrlRampTmr; - -/** Offset 0x0445 - External VNN Control Ramp Timer value - Hold off time to be used when changing the vnn_ctrl for external bypass value in us -**/ - UINT8 PchFivrExtVnnRailCtrlRampTmr; - -/** Offset 0x0446 - Set SATA DEVSLP GPIO Reset Config - Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, - 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte - for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlpResetConfig[8]; - -/** Offset 0x044E - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x044F - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x0450 - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x0451 - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x0452 - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 WatchDogEnabled; - -/** Offset 0x0453 - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x0454 - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. - Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x0455 - Reserved -**/ - UINT8 Reserved13; - -/** Offset 0x0456 - OS Timer - 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x0458 - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x045A - Force MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x045B - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[28]; - -/** Offset 0x0477 - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[28]; - -/** Offset 0x0493 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[28]; - -/** Offset 0x04AF - Reserved -**/ - UINT8 Reserved14; - -/** Offset 0x04B0 - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[28]; - -/** Offset 0x04E8 - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x04E9 - V1p05-PHY supply external FET control - Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY - supply. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcV1p05PhyExtFetControlEn; - -/** Offset 0x04EA - V1p05-IS supply external FET control - Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS - supply. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcV1p05IsExtFetControlEn; - -/** Offset 0x04EB - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x04EC - CdClock Frequency selection - 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: - 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz - 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, - 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x04ED - Enable/Disable PeiGraphicsPeimInit - <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. - Disable: FSP will NOT initialize the framebuffer. - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x04EE - Enable D3 Hot in TCSS - This policy will enable/disable D3 hot support in IOM - $EN_DIS -**/ - UINT8 D3HotEnable; - -/** Offset 0x04EF - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x04F0 - TypeC port GPIO setting - GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined - in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl - = AlderLake) -**/ - UINT32 IomTypeCPortPadCfg[8]; - -/** Offset 0x0510 - CPU USB3 Port Over Current Pin - Describe the specific over current pin number of USBC Port N. -**/ - UINT8 CpuUsb3OverCurrentPin[8]; - -/** Offset 0x0518 - Enable D3 Cold in TCSS - This policy will enable/disable D3 cold support in IOM - $EN_DIS -**/ - UINT8 D3ColdEnable; - -/** Offset 0x0519 - Enable/Disable PCIe tunneling for USB4 - Enable/Disable PCIe tunneling for USB4, default is enable - $EN_DIS -**/ - UINT8 ITbtPcieTunnelingForUsb4; - -/** Offset 0x051A - Enable/Disable SkipFspGop - Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver - $EN_DIS -**/ - UINT8 SkipFspGop; - -/** Offset 0x051B - TC State in TCSS - This TC C-State Limit in IOM -**/ - UINT8 TcCstateLimit; - -/** Offset 0x051C - Intel Graphics VBT (Video BIOS Table) Size - Size of Internal Graphics VBT Image -**/ - UINT32 VbtSize; - -/** Offset 0x0520 - Platform LID Status for LFP Displays. - LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. - 0: LidClosed, 1: LidOpen -**/ - UINT8 LidStatus; - -/** Offset 0x0521 - Reserved -**/ - UINT8 Reserved15[8]; - -/** Offset 0x0529 - Enable VMD controller - Enable/disable to VMD controller.0: Disable; 1: Enable(Default) - $EN_DIS -**/ - UINT8 VmdEnable; - -/** Offset 0x052A - Map port under VMD - Map/UnMap port under VMD - $EN_DIS -**/ - UINT8 VmdPort[31]; - -/** Offset 0x0549 - VMD Port Device - VMD Root port device number. -**/ - UINT8 VmdPortDev[31]; - -/** Offset 0x0568 - VMD Port Func - VMD Root port function number. -**/ - UINT8 VmdPortFunc[31]; - -/** Offset 0x0587 - VMD Config Bar size - Set The VMD Config Bar Size. -**/ - UINT8 VmdCfgBarSize; - -/** Offset 0x0588 - VMD Config Bar Attributes - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH -**/ - UINT8 VmdCfgBarAttr; - -/** Offset 0x0589 - VMD Mem Bar1 size - Set The VMD Mem Bar1 Size. -**/ - UINT8 VmdMemBarSize1; - -/** Offset 0x058A - VMD Mem Bar1 Attributes - 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH -**/ - UINT8 VmdMemBar1Attr; - -/** Offset 0x058B - VMD Mem Bar2 size - Set The VMD Mem Bar2 Size. -**/ - UINT8 VmdMemBarSize2; - -/** Offset 0x058C - VMD Mem Bar2 Attributes - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH -**/ - UINT8 VmdMemBar2Attr; - -/** Offset 0x058D - Reserved -**/ - UINT8 Reserved16[3]; - -/** Offset 0x0590 - VMD Variable - VMD Variable Pointer. -**/ - UINT32 VmdVariablePtr; - -/** Offset 0x0594 - Temporary CfgBar address for VMD - VMD Variable Pointer. -**/ - UINT32 VmdCfgBarBase; - -/** Offset 0x0598 - Temporary MemBar1 address for VMD - VMD Variable Pointer. -**/ - UINT32 VmdMemBar1Base; - -/** Offset 0x059C - Temporary MemBar2 address for VMD - VMD Variable Pointer. -**/ - UINT32 VmdMemBar2Base; - -/** Offset 0x05A0 - Reserved -**/ - UINT8 Reserved17; - -/** Offset 0x05A1 - Enable/Disable PMC-PD Solution - This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution - $EN_DIS -**/ - UINT8 PmcPdEnable; - -/** Offset 0x05A2 - TCSS Aux Orientation Override Enable - Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides -**/ - UINT16 TcssAuxOri; - -/** Offset 0x05A4 - TCSS HSL Orientation Override Enable - Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides -**/ - UINT16 TcssHslOri; - -/** Offset 0x05A6 - USB override in IOM - This policy will enable/disable USB Connect override in IOM - $EN_DIS -**/ - UINT8 UsbOverride; - -/** Offset 0x05A7 - ITBT Root Port Enable - ITBT Root Port Enable, 0:Disable, 1:Enable - 0:Disable, 1:Enable -**/ - UINT8 ITbtPcieRootPortEn[4]; - -/** Offset 0x05AB - TCSS USB Port Enable - Bits 0, 1, ... max Type C port control enables -**/ - UINT8 UsbTcPortEn; - -/** Offset 0x05AC - ITBTForcePowerOn Timeout value - ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. - 100 = 100 ms. -**/ - UINT16 ITbtForcePowerOnTimeoutInMs; - -/** Offset 0x05AE - ITbtConnectTopology Timeout value - ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range - is 0-10000. 100 = 100 ms. -**/ - UINT16 ITbtConnectTopologyTimeoutInMs; - -/** Offset 0x05B0 - VCCST request for IOM - This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 - $EN_DIS -**/ - UINT8 VccSt; - -/** Offset 0x05B1 - Reserved -**/ - UINT8 Reserved18; - -/** Offset 0x05B2 - ITBT DMA LTR - TCSS DMA1, DMA2 LTR value -**/ - UINT16 ITbtDmaLtr[2]; - -/** Offset 0x05B6 - Reserved -**/ - UINT8 Reserved19; - -/** Offset 0x05B7 - Enable/Disable PTM - This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports - $EN_DIS -**/ - UINT8 PtmEnabled[4]; - -/** Offset 0x05BB - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 SaPcieItbtRpLtrEnable[4]; - -/** Offset 0x05BF - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; - -/** Offset 0x05C3 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; - -/** Offset 0x05C7 - Reserved -**/ - UINT8 Reserved20; - -/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; - -/** Offset 0x05D0 - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; - -/** Offset 0x05D4 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; - -/** Offset 0x05D8 - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; - -/** Offset 0x05E0 - Force LTR Override - Force LTR Override. -**/ - UINT8 SaPcieItbtRpForceLtrOverride[4]; - -/** Offset 0x05E4 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 SaPcieItbtRpLtrConfigLock[4]; - -/** Offset 0x05E8 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x05E9 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x05EE - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x05F3 - Reserved -**/ - UINT8 Reserved21; - -/** Offset 0x05F4 - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes -**/ - UINT16 ImonSlope[5]; - -/** Offset 0x05FE - Imon offset correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b> -**/ - UINT16 ImonOffset[5]; - -/** Offset 0x0608 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x060D - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x0612 - Reserved -**/ - UINT8 Reserved22[2]; - -/** Offset 0x0614 - Thermal Design Current time window - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Range 1ms to 448s -**/ - UINT32 TdcTimeWindow[5]; - -/** Offset 0x0628 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x062D - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x062E - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/1000, - Range 0-63999. For an offset of 25.348, enter 25348. -**/ - UINT16 PsysOffset; - -/** Offset 0x0630 - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x0631 - Disable Fast Slew Rate for Deep Package C States for VR domains - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. <b>0: False</b>; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisable[5]; - -/** Offset 0x0636 - Slew Rate configuration for Deep Package C States for VR domains - Slew Rate configuration for Deep Package C States for VR domains based on Acoustic - Noise Mitigation feature enabled. ADL supports VCCIA FAST/2/4/8/16, VCCGT FAST/2/4/8 - and VCCSA FAST/2 <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRate[5]; - -/** Offset 0x063B - Reserved -**/ - UINT8 Reserved23; - -/** Offset 0x063C - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes -**/ - UINT16 TdcCurrentLimit[5]; - -/** Offset 0x0646 - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. <b>Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x0650 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b> -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x065A - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x0664 - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x066E - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x0678 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x0682 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0683 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. </b>0: Initialize; <b>1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x0684 - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0: - Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x0686 - FIVR RFI Spread Spectrum - Set the Spread Spectrum Range. <b>1.5%</b>; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, - 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% - = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0687 - Reserved -**/ - UINT8 Reserved24; - -/** Offset 0x0688 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x068C - CpuMpPpi - <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. - If not NULL, FSP will use the boot loader's implementation of multiprocessing. - See section 5.1.4 of the FSP Integration Guide for more details. -**/ - UINT32 CpuMpPpi; - -/** Offset 0x0690 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake - randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation - is enabled. Range 0-255 <b>0</b>. -**/ - UINT8 PreWake; - -/** Offset 0x0691 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up - randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation - is enabled.Range 0-255 <b>0</b>. -**/ - UINT8 RampUp; - -/** Offset 0x0692 - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down - randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation - is enabled.Range 0-255 <b>0</b>. -**/ - UINT8 RampDown; - -/** Offset 0x0693 - Reserved -**/ - UINT8 Reserved25; - -/** Offset 0x0694 - VR Voltage Limit - PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x069E - VccIn Aux Imon IccMax - PCODE MMIO Mailbox: VccIn Aux Imon IccMax. <b>0 - Auto</b> Values are in 1/4 Amp - increments. Range is 0-512. -**/ - UINT16 VccInAuxImonIccImax; - -/** Offset 0x06A0 - Reserved -**/ - UINT8 Reserved26[7]; - -/** Offset 0x06A7 - VccIn Aux Imon slope correction - PCODE MMIO Mailbox: VccIn Aux Imon slope correction. <b>0 - Auto</b> Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 VccInAuxImonSlope; - -/** Offset 0x06A8 - Reserved -**/ - UINT8 Reserved27[2]; - -/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable - Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b> -**/ - UINT8 FivrSpectrumEnable; - -/** Offset 0x06AB - Reserved -**/ - UINT8 Reserved28[13]; - -/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number - Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this - flag is set) for PPIN Support - 0: Disable, 1: Enable, 2: Auto -**/ - UINT8 PpinSupport; - -/** Offset 0x06B9 - Enable or Disable Minimum Voltage Override - Enable or disable Minimum Voltage overrides ; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 EnableMinVoltageOverride; - -/** Offset 0x06BA - Min Voltage for Runtime - PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride - = 1. Range 0 to 1999mV. <b> 0: 0mV </b> -**/ - UINT16 MinVoltageRuntime; - -/** Offset 0x06BC - Reserved -**/ - UINT8 Reserved29[2]; - -/** Offset 0x06BE - Min Voltage for C8 - PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = - 1. Range 0 to 1999mV. <b> 0: 0mV </b> -**/ - UINT16 MinVoltageC8; - -/** Offset 0x06C0 - Smbios Type4 Max Speed Override - Provide the option for platform to override the MaxSpeed field of Smbios Type 4. - If this value is not zero, it dominates the field. -**/ - UINT16 SmbiosType4MaxSpeedOverride; - -/** Offset 0x06C2 - Current root mean square - PCODE MMIO Mailbox: Current root mean square; <b>0: Disable</b>; 1: Enable.For all - VR Indexes -**/ - UINT8 Irms[5]; - -/** Offset 0x06C7 - AvxDisable - Enable or Disable AVX Support. This only applicable when all small core is disabled. - 0: Enable, 1: Disable -**/ - UINT8 AvxDisable; - -/** Offset 0x06C8 - Avx3Disable - DEPRECATED - 0: Enable, 1: Disable -**/ - UINT8 Avx3Disable; - -/** Offset 0x06C9 - Reserved -**/ - UINT8 Reserved30; - -/** Offset 0x06CA - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT8 VrPowerDeliveryDesign; - -/** Offset 0x06CB - Reserved -**/ - UINT8 Reserved31[32]; - -/** Offset 0x06EB - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x06EC - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x06F1 - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x06F6 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x0700 - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x070A - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x070B - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x070C - Enable PCH ISH SPI Cs0 pins assigned - Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. -**/ - UINT8 PchIshSpiCs0Enable[1]; - -/** Offset 0x070D - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x070E - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x070F - Enable PCH ISH SPI pins assigned - Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. -**/ - UINT8 PchIshSpiEnable[1]; - -/** Offset 0x0710 - Enable PCH ISH UART pins assigned - Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. -**/ - UINT8 PchIshUartEnable[2]; - -/** Offset 0x0712 - Enable PCH ISH I2C pins assigned - Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. -**/ - UINT8 PchIshI2cEnable[3]; - -/** Offset 0x0715 - Enable PCH ISH GP pins assigned - Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. -**/ - UINT8 PchIshGpEnable[8]; - -/** Offset 0x071D - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x071E - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x071F - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x0720 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x0721 - RTC BIOS Interface Lock - Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. - $EN_DIS -**/ - UINT8 RtcBiosInterfaceLock; - -/** Offset 0x0722 - RTC Cmos Memory Lock - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 RtcMemoryLock; - -/** Offset 0x0723 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[28]; - -/** Offset 0x073F - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[28]; - -/** Offset 0x075B - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[28]; - -/** Offset 0x0777 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[28]; - -/** Offset 0x0793 - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[28]; - -/** Offset 0x07AF - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[28]; - -/** Offset 0x07CB - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[28]; - -/** Offset 0x07E7 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[28]; - -/** Offset 0x0803 - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[28]; - -/** Offset 0x081F - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[28]; - -/** Offset 0x083B - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[28]; - -/** Offset 0x0857 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[28]; - -/** Offset 0x0873 - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[28]; - -/** Offset 0x088F - Touch Host Controller Port 0 Assignment - Assign THC Port 0 - 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 -**/ - UINT8 ThcPort0Assignment; - -/** Offset 0x0890 - Touch Host Controller Port 0 Interrupt Pin Mux - Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer - to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. -**/ - UINT32 ThcPort0InterruptPinMuxing; - -/** Offset 0x0894 - Reserved -**/ - UINT8 Reserved32; - -/** Offset 0x0895 - Touch Host Controller Port 1 Assignment - Assign THC Port 1 - 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 -**/ - UINT8 ThcPort1Assignment; - -/** Offset 0x0896 - Reserved -**/ - UINT8 Reserved33[2]; - -/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux - Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer - to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. -**/ - UINT32 ThcPort1InterruptPinMuxing; - -/** Offset 0x089C - Reserved -**/ - UINT8 Reserved34; - -/** Offset 0x089D - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; - 4: Gen4 (see: PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[28]; - -/** Offset 0x08B9 - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[28]; - -/** Offset 0x08D5 - PCIE RP Completion Timeout - The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[28]; - -/** Offset 0x08F1 - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[28]; - -/** Offset 0x090D - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[28]; - -/** Offset 0x0929 - Reserved -**/ - UINT8 Reserved35[28]; - -/** Offset 0x0945 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[28]; - -/** Offset 0x0961 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[28]; - -/** Offset 0x097D - PCIe override default settings for EQ - Choose PCIe EQ method - $EN_DIS -**/ - UINT8 PcieEqOverrideDefault; - -/** Offset 0x097E - PCIe choose EQ method - Choose PCIe EQ method - 0: HardwareEq, 1: FixedEq -**/ - UINT8 PcieEqMethod; - -/** Offset 0x097F - PCIe choose EQ mode - Choose PCIe EQ mode - 0: PresetEq, 1: CoefficientEq -**/ - UINT8 PcieEqMode; - -/** Offset 0x0980 - PCIe EQ local transmitter override - Enable/Disable local transmitter override - $EN_DIS -**/ - UINT8 PcieEqLocalTransmitterOverrideEnable; - -/** Offset 0x0981 - PCIe number of valid list entries - Select number of presets or coefficients depending on the mode -**/ - UINT8 PcieEqPh3NumberOfPresetsOrCoefficients; - -/** Offset 0x0982 - PCIe pre-cursor coefficient list - Provide a list of pre-cursor coefficients to be used during phase 3 EQ -**/ - UINT8 PcieEqPh3PreCursorList[10]; - -/** Offset 0x098C - PCIe post-cursor coefficient list - Provide a list of post-cursor coefficients to be used during phase 3 EQ -**/ - UINT8 PcieEqPh3PostCursorList[10]; - -/** Offset 0x0996 - PCIe preset list - Provide a list of presets to be used during phase 3 EQ -**/ - UINT8 PcieEqPh3PresetList[11]; - -/** Offset 0x09A1 - Reserved -**/ - UINT8 Reserved36[3]; - -/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset - Allows to select the downstream port preset value that will be used during phase - 1 of equalization -**/ - UINT32 PcieEqPh1DownstreamPortTransmitterPreset; - -/** Offset 0x09A8 - PCIe EQ phase 1 upstream tranmitter port preset - Allows to select the upstream port preset value that will be used during phase 1 - of equalization -**/ - UINT32 PcieEqPh1UpstreamPortTransmitterPreset; - -/** Offset 0x09AC - PCIe EQ phase 2 local transmitter override preset - Allows to select the value of the preset used during phase 2 local transmitter override -**/ - UINT8 PcieEqPh2LocalTransmitterOverridePreset; - -/** Offset 0x09AD - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite[28]; - -/** Offset 0x09C9 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x09CA - PCIE Rp Function Swap - DEPRECATED. Allows BIOS to use root port function number swapping when root port - of function 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x09CB - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets - Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 CpuPcieGen3ProgramStaticEq; - -/** Offset 0x09CC - Enable/Disable GEN4 Static EQ Phase1 programming - Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets - Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 CpuPcieGen4ProgramStaticEq; - -/** Offset 0x09CD - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x09CE - PCIE IMR - Enables Isolated Memory Region for PCIe. - $EN_DIS -**/ - UINT8 PcieRpImrEnabled; - -/** Offset 0x09CF - PCIE IMR port number - Selects PCIE root port number for IMR feature. -**/ - UINT8 PcieRpImrSelection; - -/** Offset 0x09D0 - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x09D1 - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x09D2 - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x09D3 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x09D4 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x09D5 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x09D6 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x09D7 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x09D8 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x09D9 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x09DA - USB Overcurrent Override for VISA - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when VISA pin is muxed with USB OC - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x09DB - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x09DC - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x09DD - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x09DE - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x09DF - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x09E0 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x09E1 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x09E2 - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x09E3 - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x09E4 - PCH Legacy IO Low Latency Enable - Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x09E5 - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x09E6 - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x09E7 - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x09E8 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x09F0 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x09F8 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x0A00 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x0A08 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x0A10 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x0A18 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x0A20 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x0A30 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x0A38 - PCH Sata Rst Raid Alternate Id - Enable RAID Alternate ID. - $EN_DIS -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x0A39 - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x0A3C - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x0A3F - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x0A42 - UFS enable/disable - Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller - 0 and (0,1) to enable controller 1 - $EN_DIS -**/ - UINT8 UfsEnable[2]; - -/** Offset 0x0A44 - IEH Mode - Integrated Error Handler Mode, 0: Bypass, 1: Enable - 0: Bypass, 1:Enable -**/ - UINT8 IehMode; - -/** Offset 0x0A45 - Reserved -**/ - UINT8 Reserved37; - -/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x0A48 - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x0A4A - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x0A4C - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x0A4D - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x0A4E - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x0A4F - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x0A50 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x0A51 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x0A52 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x0A53 - Thermal Sensor 0 Target Width - Thermal Sensor 0 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x0A54 - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x0A55 - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x0A56 - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x0A57 - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x0A58 - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x0A59 - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x0A5A - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x0A5B - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x0A5C - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x0A5D - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x0A5E - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x0A5F - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x0A60 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x0A61 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x0A62 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x0A63 - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x0A64 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x0A65 - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x0A67 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x0A69 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x0A6B - Reserved -**/ - UINT8 Reserved38; - -/** Offset 0x0A6C - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x0A6E - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x0A7E - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x0A88 - Enable xHCI LTR override - Enables override of recommended LTR values for xHCI - $EN_DIS -**/ - UINT8 PchUsbLtrOverrideEnable; - -/** Offset 0x0A89 - Reserved -**/ - UINT8 Reserved39[3]; - -/** Offset 0x0A8C - xHCI High Idle Time LTR override - Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting -**/ - UINT32 PchUsbLtrHighIdleTimeOverride; - -/** Offset 0x0A90 - xHCI Medium Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting -**/ - UINT32 PchUsbLtrMediumIdleTimeOverride; - -/** Offset 0x0A94 - xHCI Low Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting -**/ - UINT32 PchUsbLtrLowIdleTimeOverride; - -/** Offset 0x0A98 - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x0A99 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x0A9A - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x0A9B - Hybrid Storage Detection and Configuration Mode - Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. - Default is 0: Disabled - 0: Disabled, 1: Dynamic Configuration -**/ - UINT8 HybridStorageMode; - -/** Offset 0x0A9C - Reserved -**/ - UINT8 Reserved40[4]; - -/** Offset 0x0AA0 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0AC0 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x0AC4 - Reserved -**/ - UINT8 Reserved41[4]; - -/** Offset 0x0AC8 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0AD0 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x0AD8 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x0AD9 - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x0ADA - Skip Ssid Programming. - When set to TRUE, silicon code will not do any SSID programming and platform code - needs to handle that by itself properly. - $EN_DIS -**/ - UINT8 SiSkipSsidProgramming; - -/** Offset 0x0ADB - Reserved -**/ - UINT8 Reserved42; - -/** Offset 0x0ADC - Change Default SVID - Change the default SVID used in FSP to programming internal devices. This is only - valid when SkipSsidProgramming is FALSE. -**/ - UINT16 SiCustomizedSvid; - -/** Offset 0x0ADE - Change Default SSID - Change the default SSID used in FSP to programming internal devices. This is only - valid when SkipSsidProgramming is FALSE. -**/ - UINT16 SiCustomizedSsid; - -/** Offset 0x0AE0 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. This is - only valid when SkipSsidProgramming is FALSE. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x0AE4 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. - This is only valid when SkipSsidProgramming is FALSE. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x0AE6 - USB2 Port Reset Message Enable - 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must - be enable for USB2 Port those are paired with CPU XHCI Port -**/ - UINT8 PortResetMessageEnable[16]; - -/** Offset 0x0AF6 - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x0AF7 - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x0AF8 - Enforce Enhanced Debug Mode - Determine if ME should enter Enhanced Debug Mode. <b>0: disable</b>, 1: enable - $EN_DIS -**/ - UINT8 EnforceEDebugMode; - -/** Offset 0x0AF9 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x0AFA - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x0AFB - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmL1</b> - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x0AFC - PchDmiCwbEnable - Central Write Buffer feature configurable and enabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x0AFD - OS IDLE Mode Enable - Enable/Disable OS Idle Mode - $EN_DIS -**/ - UINT8 PmcOsIdleEnable; - -/** Offset 0x0AFE - S0ix Auto-Demotion - Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. - $EN_DIS -**/ - UINT8 PchS0ixAutoDemotion; - -/** Offset 0x0AFF - Latch Events C10 Exit - When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are - captured on C10 exit (instead of C10 entry which is default) - $EN_DIS -**/ - UINT8 PchPmLatchEventsC10Exit; - -/** Offset 0x0B00 - Reserved -**/ - UINT8 Reserved43[12]; - -/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm - CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 CpuPcieEqPh3LaneParamCm[32]; - -/** Offset 0x0B2C - PCIE Eq Ph3 Lane Param Cp - CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 CpuPcieEqPh3LaneParamCp[32]; - -/** Offset 0x0B4C - Gen3 Root port preset values per lane - Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default - for each lane -**/ - UINT8 CpuPcieGen3RootPortPreset[20]; - -/** Offset 0x0B60 - Pcie Gen4 Root port preset values per lane - Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default - for each lane -**/ - UINT8 CpuPcieGen4RootPortPreset[20]; - -/** Offset 0x0B74 - Pcie Gen3 End port preset values per lane - Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default - for each lane -**/ - UINT8 CpuPcieGen3EndPointPreset[20]; - -/** Offset 0x0B88 - Pcie Gen4 End port preset values per lane - Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default - for each lane -**/ - UINT8 CpuPcieGen4EndPointPreset[20]; - -/** Offset 0x0B9C - Pcie Gen3 End port Hint values per lane - Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 CpuPcieGen3EndPointHint[20]; - -/** Offset 0x0BB0 - Pcie Gen4 End port Hint values per lane - Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 CpuPcieGen4EndPointHint[20]; - -/** Offset 0x0BC4 - CPU PCIe Fia Programming - Load Fia configuration if enable. 0: Disable; 1: Enable(Default). - $EN_DIS -**/ - UINT8 CpuPcieFiaProgramming; - -/** Offset 0x0BC5 - CPU PCIe RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable(Default). - $EN_DIS -**/ - UINT8 CpuPcieClockGating[4]; - -/** Offset 0x0BC9 - CPU PCIe RootPort Power Gating - Describes whether the PCI Express Power Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable(Default). - $EN_DIS -**/ - UINT8 CpuPciePowerGating[4]; - -/** Offset 0x0BCD - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 CpuPcieComplianceTestMode; - -/** Offset 0x0BCE - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 CpuPcieEnablePeerMemoryWrite; - -/** Offset 0x0BCF - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 CpuPcieRpFunctionSwap; - -/** Offset 0x0BD0 - PCI Express Slot Selection - Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default). - $EN_DIS -**/ - UINT8 CpuPcieSlotSelection; - -/** Offset 0x0BD1 - Reserved -**/ - UINT8 Reserved44[3]; - -/** Offset 0x0BD4 - CPU PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 CpuPcieDeviceOverrideTablePtr; - -/** Offset 0x0BD8 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 CpuPcieRpHotPlug[4]; - -/** Offset 0x0BDC - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 CpuPcieRpPmSci[4]; - -/** Offset 0x0BE0 - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 CpuPcieRpTransmitterHalfSwing[4]; - -/** Offset 0x0BE4 - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 CpuPcieRpAcsEnabled[4]; - -/** Offset 0x0BE8 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 CpuPcieRpEnableCpm[4]; - -/** Offset 0x0BEC - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 CpuPcieRpAdvancedErrorReporting[4]; - -/** Offset 0x0BF0 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 CpuPcieRpUnsupportedRequestReport[4]; - -/** Offset 0x0BF4 - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 CpuPcieRpFatalErrorReport[4]; - -/** Offset 0x0BF8 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 CpuPcieRpNoFatalErrorReport[4]; - -/** Offset 0x0BFC - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 CpuPcieRpCorrectableErrorReport[4]; - -/** Offset 0x0C00 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 CpuPcieRpSystemErrorOnFatalError[4]; - -/** Offset 0x0C04 - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 CpuPcieRpSystemErrorOnNonFatalError[4]; - -/** Offset 0x0C08 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 CpuPcieRpSystemErrorOnCorrectableError[4]; - -/** Offset 0x0C0C - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD. -**/ - UINT8 CpuPcieRpMaxPayload[4]; - -/** Offset 0x0C10 - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT8 CpuPcieRpDpcEnabled[4]; - -/** Offset 0x0C14 - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT8 CpuPcieRpDpcExtensionsEnabled[4]; - -/** Offset 0x0C18 - CPU PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 CpuPcieRpSlotImplemented[4]; - -/** Offset 0x0C1C - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 CpuPcieRpGen3EqPh3Method[4]; - -/** Offset 0x0C20 - PCIE RP Gen4 Equalization Phase Method - PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 CpuPcieRpGen4EqPh3Method[4]; - -/** Offset 0x0C24 - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 CpuPcieRpPhysicalSlotNumber[4]; - -/** Offset 0x0C28 - PCIE RP Aspm - The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable; - 1: CpuPcieAspmL0s; 2: CpuPcieAspmL1; 3:CpuPcieAspmL0sL1(Default) -**/ - UINT8 CpuPcieRpAspm[4]; - -/** Offset 0x0C2C - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). - Default is CpuPcieL1SubstatesL1_1_2. -**/ - UINT8 CpuPcieRpL1Substates[4]; - -/** Offset 0x0C30 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 CpuPcieRpLtrEnable[4]; - -/** Offset 0x0C34 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 CpuPcieRpLtrConfigLock[4]; - -/** Offset 0x0C38 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT8 CpuPcieRpPtmEnabled[4]; - -/** Offset 0x0C3C - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 CpuPcieRpDetectTimeoutMs[4]; - -/** Offset 0x0C44 - Multi-VC for PCIE RP Mask - Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT8 CpuPcieRpMultiVcEnabled[4]; - -/** Offset 0x0C48 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTranEnable[10]; - -/** Offset 0x0C52 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default - = 4Ch</b>. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTran[10]; - -/** Offset 0x0C5C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTranEnable[10]; - -/** Offset 0x0C66 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], - <b>Default = 4Ch</b>. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTran[10]; - -/** Offset 0x0C70 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTranEnable[10]; - -/** Offset 0x0C7A - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], - <b>Default = 4Ch</b>. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTran[10]; - -/** Offset 0x0C84 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTranEnable[10]; - -/** Offset 0x0C8E - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], - <b>Default = 4Ch</b>. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTran[10]; - -/** Offset 0x0C98 - Skip PAM regsiter lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x0C99 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x0C9A - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x0C9B - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x0C9C - Enable/Disable CdynmaxClamp - Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x0C9D - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x0C9E - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x0C9F - Enable/Disable CdClock Init - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock if not initialized by Gfx PEIM - $EN_DIS -**/ - UINT8 SkipCdClockInit; - -/** Offset 0x0CA0 - Enable RC1p frequency request to PMA (provided all other conditions are met) - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 RC1pFreqEnable; - -/** Offset 0x0CA1 - Enable TSN Multi-VC - Enable/disable Multi Virtual Channels(VC) in TSN. - $EN_DIS -**/ - UINT8 PchTsnMultiVcEnable; - -/** Offset 0x0CA2 - Reserved -**/ - UINT8 Reserved45[2]; - -/** Offset 0x0CA4 - LogoPixelHeight Address - Address of LogoPixelHeight -**/ - UINT32 LogoPixelHeight; - -/** Offset 0x0CA8 - LogoPixelWidth Address - Address of LogoPixelWidth -**/ - UINT32 LogoPixelWidth; - -/** Offset 0x0CAC - Reserved -**/ - UINT8 Reserved46[5]; - -/** Offset 0x0CB1 - RSR feature - Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b> - $EN_DIS -**/ - UINT8 EnableRsr; - -/** Offset 0x0CB2 - Reserved -**/ - UINT8 Reserved47[4]; - -/** Offset 0x0CB6 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x0CB7 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x0CB8 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) - 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x0CB9 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x0CBA - Turbo settings Lock - Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x0CBB - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x0CBC - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x0CBD - Package PL3 Lock - Package PL3 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x0CBE - Package PL4 Lock - Package PL4 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x0CBF - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For SKL Y SKU, the recommended default for this policy is - <b>10</b>, For all other SKUs the recommended default are <b>0</b> -**/ - UINT8 TccActivationOffset; - -/** Offset 0x0CC0 - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>, - For all other SKUs the recommended default are <b>0: Disabled</b>. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x0CC1 - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; <b>0: Disabled</b>; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x0CC2 - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x0CC3 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x0CC4 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x0CC5 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x0CC6 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x0CC7 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x0CC8 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x0CC9 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x0CCA - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x0CCB - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x0CCC - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x0CCD - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x0CCE - PL1 Enable value - PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x0CCF - PL1 timewindow - PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 - , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x0CD0 - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x0CD1 - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x0CD2 - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x0CD3 - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0CD4 - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x0CD5 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x0CD6 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x0CD7 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x0CD8 - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0CD9 - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - <b>1: Enable</b> - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x0CDA - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. <b>0: Disable</b>; 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0CDB - Enable or Disable T states - Enable or Disable T states; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0CDC - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x0CDD - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x0CDE - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x0CDF - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x0CE0 - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 EnableAllThermalFunctions; - -/** Offset 0x0CE1 - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x0CE2 - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x0CE3 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x0CE4 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x0CE5 - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0CE6 - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0CE7 - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x0CE8 - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x0CE9 - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0CEA - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0CEB - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0CEC - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x0CED - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x0CEE - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x0CEF - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x0CF0 - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x0CF1 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: - No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x0CF2 - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable;<b> 1: Enable</b> - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x0CF3 - Configuration for boot TDP selection - Deprecated. Move to premem. -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x0CF4 - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x0CF5 - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x0D1D - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x0D2D - Reserved -**/ - UINT8 Reserved48; - -/** Offset 0x0D2E - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x0D30 - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x0D32 - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x0D34 - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0D36 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0D38 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x0D3A - Reserved -**/ - UINT8 Reserved49[2]; - -/** Offset 0x0D3C - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0D40 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x0D44 - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0D48 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x0D4C - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0D50 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x0D54 - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0D58 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x0D5C - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x0D60 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x0D64 - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x0D68 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x0D6C - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x0D70 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x0D71 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; <b>0: False</b>; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x0D72 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x0D73 - Reserved -**/ - UINT8 Reserved50[4]; - -/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b> - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x0D78 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x0D79 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x0D7A - Minimum Ring ratio limit override - Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x0D7B - Maximum Ring ratio limit override - Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x0D7C - Enable or Disable Per Core P State OS control - Enable or Disable Per Core P State OS control. 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 EnablePerCorePState; - -/** Offset 0x0D7D - Enable or Disable HwP Autonomous Per Core P State OS control - Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; <b>1: - Enable</b> - $EN_DIS -**/ - UINT8 EnableHwpAutoPerCorePstate; - -/** Offset 0x0D7E - Enable or Disable HwP Autonomous EPP Grouping - Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 EnableHwpAutoEppGrouping; - -/** Offset 0x0D7F - Enable or Disable EPB override over PECI - Enable or Disable EPB override over PECI. <b>0: Disable;</b> 1: Enable - $EN_DIS -**/ - UINT8 EnableEpbPeciOverride; - -/** Offset 0x0D80 - Enable or Disable Fast MSR for IA32_HWP_REQUEST - Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;<b> 1: Enable</b> - $EN_DIS -**/ - UINT8 EnableFastMsrHwpReq; - -/** Offset 0x0D81 - Enable Configurable TDP - Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP; - <b>1: Applies to cTDP</b> - $EN_DIS -**/ - UINT8 ApplyConfigTdp; - -/** Offset 0x0D82 - Reserved -**/ - UINT8 Reserved51; - -/** Offset 0x0D83 - Dual Tau Boost - Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0: - Disable</b>; 1: Enable - $EN_DIS -**/ - UINT8 DualTauBoost; - -/** Offset 0x0D84 - Reserved -**/ - UINT8 Reserved52[32]; - -/** Offset 0x0DA4 - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): - EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE - 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x0DA5 - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x0DA6 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0DA7 - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x0DA8 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x0DA9 - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x0DAA - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x0DAB - Reserved -**/ - UINT8 Reserved53; - -/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[28]; - -/** Offset 0x0DE4 - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[28]; - -/** Offset 0x0E1C - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[28]; - -/** Offset 0x0E38 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[28]; - -/** Offset 0x0E54 - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[28]; - -/** Offset 0x0E8C - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[28]; - -/** Offset 0x0EA8 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28]; - -/** Offset 0x0EC4 - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[28]; - -/** Offset 0x0EFC - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[28]; - -/** Offset 0x0F18 - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[28]; - -/** Offset 0x0F50 - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0F51 - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0F52 - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0F53 - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0F54 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0F55 - Low Power Mode Enable/Disable config mask - Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds - to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, - LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. -**/ - UINT8 PmcLpmS0ixSubStateEnableMask; - -/** Offset 0x0F56 - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 CpuPcieRpLtrMaxSnoopLatency[4]; - -/** Offset 0x0F5E - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4]; - -/** Offset 0x0F66 - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 CpuPcieRpSnoopLatencyOverrideMode[4]; - -/** Offset 0x0F6A - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4]; - -/** Offset 0x0F6E - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 CpuPcieRpSnoopLatencyOverrideValue[4]; - -/** Offset 0x0F76 - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4]; - -/** Offset 0x0F7A - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4]; - -/** Offset 0x0F7E - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4]; - -/** Offset 0x0F86 - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 CpuPcieRpGen3Uptp[4]; - -/** Offset 0x0F8A - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 CpuPcieRpGen3Dptp[4]; - -/** Offset 0x0F8E - PCIE RP Upstream Port Transmiter Preset - Used during Gen4 Link Equalization. Used for all lanes. Default is 8. -**/ - UINT8 CpuPcieRpGen4Uptp[4]; - -/** Offset 0x0F92 - PCIE RP Downstream Port Transmiter Preset - Used during Gen4 Link Equalization. Used for all lanes. Default is 9. -**/ - UINT8 CpuPcieRpGen4Dptp[4]; - -/** Offset 0x0F96 - Reserved -**/ - UINT8 Reserved54[16]; - -/** Offset 0x0FA6 - FOMS Control Policy - Choose the Foms Control Policy, <b>Default = 0 </b> - 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms -**/ - UINT8 CpuPcieFomsCp[4]; - -/** Offset 0x0FAA - PMC C10 dynamic threshold dajustment enable - Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs - $EN_DIS -**/ - UINT8 PmcC10DynamicThresholdAdjustment; - -/** Offset 0x0FAB - P2P mode for PCIE RP - Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable. - 0: Disable, 1: Enable -**/ - UINT8 CpuPcieRpPeerToPeerMode[4]; - -/** Offset 0x0FAF - Reserved -**/ - UINT8 Reserved55[33]; - -/** Offset 0x0FD0 - FspEventHandler - <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER. -**/ - UINT32 FspEventHandler; - -/** Offset 0x0FD4 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x0FD5 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x0FD6 - Use DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 EmmcUseCustomDlls; - -/** Offset 0x0FD7 - Reserved -**/ - UINT8 Reserved56; - -/** Offset 0x0FD8 - Emmc Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 EmmcTxCmdDelayRegValue; - -/** Offset 0x0FDC - Emmc Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 EmmcTxDataDelay1RegValue; - -/** Offset 0x0FE0 - Emmc Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 EmmcTxDataDelay2RegValue; - -/** Offset 0x0FE4 - Emmc Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay1RegValue; - -/** Offset 0x0FE8 - Emmc Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay2RegValue; - -/** Offset 0x0FEC - Emmc Rx Strobe Delay control register value - Please see Rx Strobe Delay control register definition for help -**/ - UINT32 EmmcRxStrobeDelayRegValue; - -/** Offset 0x0FF0 - Reserved -**/ - UINT8 Reserved57[69]; - -/** Offset 0x1035 - Enable VMD Global Mapping - Enable/disable to VMD controller.0: Disable; 1: Enable(Default) - $EN_DIS -**/ - UINT8 VmdGlobalMapping; - -/** Offset 0x1036 - Reserved -**/ - UINT8 Reserved58[138]; -} FSP_S_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPS_ARCH_UPD FspsArchUpd; - -/** Offset 0x0040 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x10C0 -**/ - UINT8 UnusedUpdSpace44[6]; - -/** Offset 0x10C6 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h deleted file mode 100644 index 73a8d29cfe..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h +++ /dev/null @@ -1,320 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.<BR> - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License that accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php. - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -@par Specification Reference: -**/ -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 2 -#define MAX_CH 4 -#define MAX_DIMM 2 -// Must match definitions in -// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h -#define HOB_MAX_SAGV_POINTS 4 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -// @todo remove and use the MdePkg\Include\Pi\PiHob.h -#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) -#ifndef __HOB__H__ -typedef struct _EFI_HOB_GENERIC_HEADER { - UINT16 HobType; - UINT16 HobLength; - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -typedef struct _EFI_HOB_GUID_TYPE { - EFI_HOB_GENERIC_HEADER Header; - EFI_GUID Name; - /// - /// Guid specific data goes here - /// -} EFI_HOB_GUID_TYPE; -#endif -#endif - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef __MRC_BOOT_MODE__ -#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h - #ifndef INT32_MAX - #define INT32_MAX (0x7FFFFFFF) - #endif //INT32_MAX -typedef enum { - bmCold, ///< Cold boot - bmWarm, ///< Warm boot - bmS3, ///< S3 resume - bmFast, ///< Fast boot - MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. - MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. -} MRC_BOOT_MODE; -#endif //__MRC_BOOT_MODE__ - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR5 -#define MRC_DDR_TYPE_DDR5 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR5 -#define MRC_DDR_TYPE_LPDDR5 2 -#endif -#ifndef MRC_DDR_TYPE_LPDDR4 -#define MRC_DDR_TYPE_LPDDR4 3 -#endif -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 4 -#endif - -#define MAX_PROFILE_NUM 7 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported - -#define MAX_TRACE_REGION 5 -#define MAX_TRACE_CACHE_TYPE 2 - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay -} MRC_IP_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz - UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. -} CONTROLLER_INFO; - -typedef struct { - UINT64 BaseAddress; ///< Trace Base Address - UINT64 TotalSize; ///< Total Trace Region of Same Cache type - UINT8 CacheType; ///< Trace Cache Type - UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code - UINT8 Rsvd[2]; -} PSMI_MEM_INFO; - -/// This data structure contains per-SaGv timing values that are considered output by the MRC. -typedef struct { - UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s - MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec - MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific -} HOB_SAGV_TIMING_OUT; - -/// This data structure contains SAGV config values that are considered output by the MRC. -typedef struct { - UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. - UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. - HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; -} HOB_SAGV_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT8 IsDMBRunning; ///< Deprecated. - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - /// - /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. - /// Bit 0: XMP Profile 1 capability status - /// Bit 1: XMP Profile 2 capability status - /// Bit 2: XMP Profile 3 capability status - /// Bit 3: User Profile 4 capability status - /// Bit 4: User Profile 5 capability status - /// - UINT8 XmpProfileEnable; - UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed - UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - UINT32 VddqVoltage[MAX_PROFILE_NUM]; - UINT32 VppVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; - UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 - UINT32 NumPopulatedChannels; ///< Total number of memory channels populated - HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. - UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels - BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population - BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config - BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - <b>Revision 1:</b> - - Initial version. - <b>Revision 2:</b> - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT64 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; - PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; - PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; - BOOLEAN MrcBasicMemoryTestPass; -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ |