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authorUsha P <usha.p@intel.com>2021-11-30 11:27:38 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-03 21:29:37 +0000
commit78c9b678d74ae9acd9ce04136706c7915cd34097 (patch)
treed131317e6aa618199afb44c58063fca393914527
parent7e7cc1a8c9a87e33bd772e8526734c7a82ec2db7 (diff)
soc/intel/alderlake: Add support for ADL-N PCH
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to specify the correct amount of PCIe I/O. Document number 645550 indicates that Alder Lake-N has 12 PCH root ports and no CPU root ports. Document number 645548 indicates ADL-N has 5 clock sources and 5 clock request signals. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/soc/intel/alderlake/Kconfig10
-rw-r--r--src/soc/intel/alderlake/include/soc/bootblock.h1
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 2f8f3da429..9fe2668899 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -11,6 +11,12 @@ config SOC_INTEL_ALDERLAKE_PCH_M
help
Choose this option if your mainboard has a PCH-M chipset.
+config SOC_INTEL_ALDERLAKE_PCH_N
+ bool
+ select SOC_INTEL_ALDERLAKE
+ help
+ Choose this option if your mainboard has a PCH-N chipset.
+
config SOC_INTEL_ALDERLAKE_PCH_P
bool
select SOC_INTEL_ALDERLAKE
@@ -178,11 +184,13 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 12 if SOC_INTEL_ALDERLAKE_PCH_N
default 12 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 0 if SOC_INTEL_ALDERLAKE_PCH_N
default 3 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_ROOT_PORTS
@@ -192,11 +200,13 @@ config MAX_ROOT_PORTS
config MAX_PCIE_CLOCK_SRC
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 7 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_PCIE_CLOCK_REQ
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
config SMM_TSEG_SIZE
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 059568d09b..ce2e42e6b2 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -4,6 +4,7 @@
#define _SOC_ALDERLAKE_BOOTBLOCK_H_
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \
+ CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \
CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
#error "Please select exactly one PCH type"
#endif