diff options
| author | Liju-Clr Chen <liju-clr.chen@mediatek.com> | 2022-11-01 13:14:13 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-04 13:18:53 +0000 |
| commit | 78b7fb2c17a697e7511a48a271402839f51e7800 (patch) | |
| tree | 3da1f33f900415d0ee8750223f4748e3c6993345 | |
| parent | 0feb5ce0c8cbe3fb3ef119a7af285c8b8914251f (diff) | |
soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
When enabling cpufreq-hw driver, it is required for MCUPM to access
secure registers. Therefore, we enable side-band to allow MCUPM to
access the secure registers.
BUG=b:236331463
TEST=It works well after boot to login shell.
Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
| -rw-r--r-- | src/soc/mediatek/mt8188/devapc.c | 5 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/devapc.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 1fe3cf8626..afb39d5919 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1550,7 +1550,10 @@ static void dump_peri_par_ao_apc(uintptr_t base) static void infra_init(uintptr_t base) { - /* Default APC setting */ + /* Side-band */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), MCUPM_SEC, SECURE_TRANS); + + /* TODO: Setup SCP, SSPM and MCUPM permissions in APC . */ set_infra_ao_apc(base); } diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h index e0b0f00ccf..3cbce5c417 100644 --- a/src/soc/mediatek/mt8188/include/soc/devapc.h +++ b/src/soc/mediatek/mt8188/include/soc/devapc.h @@ -17,6 +17,8 @@ enum devapc_ao_offset { AO_APC_CON = 0x00F00, }; +DEFINE_BIT(MCUPM_SEC, 1) + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ |