AMD Steppe Eagle: update vendorcode header files to MullinsPI 1.0.0.A

This is required the BLOB change I67817dc59
AMD Steppe Eagle: Update to  MullinsPI 1.0.0.A (Binary PI 1.1).

This is tested on Olive Hill Plus. The board can boot to Windows 7.
PCIe slot, USB and NIC work.

Change-Id: I605df26b61bdffabd74846206ad0b7bf677ebed1
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11225
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 29 insertions, 0 deletions

diff --git a/src/vendorcode/amd/pi/00730F01/AGESA.h b/src/vendorcode/amd/pi/00730F01/AGESA.h
index 8132c615fb..c25b631cb2 100644
--- a/src/vendorcode/amd/pi/00730F01/AGESA.h
+++ b/src/vendorcode/amd/pi/00730F01/AGESA.h
@@ -775,6 +775,17 @@ typedef enum {
   DP_VS_0_4V_9_5DB = 0x18                                 ///< 0x18
 } DP_FIXED_VOLT_SWING_TYPE;
 
+/// Alternative DRAM MAC
+typedef enum {
+  MAC_UNTESTEDMAC,                               ///< Assign 0 to Untested MAC
+  MAC_700k,                                      ///< Assign 1 to 700k
+  MAC_600k,                                      ///< Assign 2 to 600k
+  MAC_500k,                                      ///< Assign 3 to 500k
+  MAC_400k,                                      ///< Assign 4 to 400k
+  MAC_300k,                                      ///< Assign 5 to 300k
+  MAC_200k,                                      ///< Assign 6 to 200k
+} DRAM_MAXIMUM_ACTIVATE_COUNT;
+
 // Macro for statically initializing various structures
 #define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
 #define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
@@ -1536,6 +1547,7 @@ typedef struct _CH_TIMING_STRUCT {
                                   ///<  667 (MHz)
                                   ///<  800 (MHz)
                                   ///<  and so on...
+  OUT UINT8   Mac;                ///< Maximum Activate Count
   OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
   OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
   OUT UINT8   Trp;                ///< DCT Trp (busclocks)
@@ -1791,6 +1803,21 @@ typedef struct _MEM_PARAMETER_STRUCT {
                                    ///<
                                    ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
 
+  // Dram Mac Default
+
+  IN  UINT8 DramMacDefault;  ///< Default Maximum Activate Count
+                             ///<
+                             ///< @BldCfgItem{BLDCFG_MEMORY_ALTERNATIVE_MAX_ACTIVATE_COUNT}
+
+  // Dram Extended Temperature Range
+
+  IN  BOOLEAN EnableExtendedTemperatureRange; ///< enable extended temperature support.
+                              ///<   - FALSE =disable (default)
+                              ///<   - TRUE =enable
+                             ///<
+                             ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE}
+                             // Extended temperature range
+
   // Online Spare
 
   IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
@@ -2694,6 +2721,8 @@ typedef struct {
   IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
   IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
   IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
+  IN UINT8   CfgMemoryMacDefault;                 ///< Memory DRAM MAC Default
+  IN BOOLEAN CfgMemoryExtendedTemperatureRange;   ///< Memory Extended Temperature Range
   IN UINT32  CfgPowerDownMode;                    ///< Power Down Mode.
   IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
   IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.