treewide,intel/skylake: Use boolean type for s0ix_enable dt option

Using the boolean type and the true/false macros give the reader a
better understanding about the option. Thus, use the bool type for the
attribute and use the macros for assignments.

Skylake mainboards which use that option were changed by the following
command ran from the root directory.

    socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \
    option="s0ix_enable" && \
    grep -Er "${socs}" src/mainboard | \
        cut -d ':' -f 1 | \
        awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \
        xargs grep -r "${option}" | \
        cut -d ':' -f 1 | \
        xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g"

Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

12 files changed, 13 insertions, 12 deletions

diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
index 38a56cad77..1521501e70 100644
--- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
+++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -311,7 +311,7 @@ chip soc/intel/skylake
 			register "gpe0_dw2" = "GPP_E"	# 11:8 in pwrmbase+0120h
 
 			# Enable S0ix
-			register "s0ix_enable" = "1"
+			register "s0ix_enable" = true
 
 			register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"	# 11:10 in A4h-A7h
 			register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"	# 5:4 in A4h-A7h
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 74c601a58f..e19e2386b2 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -62,7 +62,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# FSP Configuration
 	register "SataSalpSupport" = "0"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 4c759f6d04..ee3c86bdc1 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -37,7 +37,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# Disable Command TriState
 	register "CmdTriStateDis" = "1"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 2e3953ad4f..717ab547cd 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# FSP Configuration
 	register "SataSalpSupport" = "0"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index aa905d105b..6a34241dc2 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# FSP Configuration
 	register "SataSalpSupport" = "0"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 07363fd0c5..27a9bb9f50 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# FSP Configuration
 	register "SataSalpSupport" = "0"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index b381a253a5..5f322b12e8 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -30,7 +30,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# Disable Command TriState
 	register "CmdTriStateDis" = "1"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 8be97c8c36..bc2d4a0f8c 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -37,7 +37,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# Disable Command TriState
 	register "CmdTriStateDis" = "1"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index a20c197537..fbe6c1f21d 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	# FSP Configuration
 	register "SataSalpSupport" = "0"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 4e4cbac04a..1f17fb1358 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -6,7 +6,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_ac" = "1"
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = true
 
 	register "gpe0_dw0" = "GPP_B"
 	register "gpe0_dw1" = "GPP_D"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index b4a08bf418..76f75800b3 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -20,7 +20,7 @@ chip soc/intel/skylake
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
 	# Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
-	register "s0ix_enable"			= "1"
+	register "s0ix_enable"			= true
 	register "PmConfigSlpS3MinAssert"	= "SLP_S3_MIN_ASSERT_50MS"
 	register "PmConfigSlpS4MinAssert"	= "SLP_S4_MIN_ASSERT_4S"
 	register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index ce8712ca69..af6212ed5a 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -12,6 +12,7 @@
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/power_limit.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include <soc/gpe.h>
 #include <soc/irq.h>
@@ -56,7 +57,7 @@ struct soc_intel_skylake_config {
 	uint32_t gen4_dec;
 
 	/* Enable S0iX support */
-	int s0ix_enable;
+	bool s0ix_enable;
 
 	/* Enable DPTF support */
 	int dptf_enable;