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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-17 23:00:31 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-02 04:51:02 +0000 |
| commit | 7369e83de1e42138245e728304dc743feaa08c32 (patch) | |
| tree | f3b65393ed1f4c46f4abda8c5a23284bc43c792e | |
| parent | fb32be4090f088da8db877d3dce42d95b50212b6 (diff) | |
AGESA: Add romstage timestamps
Experiments on f14 f15tn and 16kb suggest that TSC
counter value shifts at end of raminit. To account
for this all previously stored values in timestamp
table are also divided by 4.
Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/cpu/amd/agesa/romstage.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c index cb98e7b6d3..a7d2ff90b7 100644 --- a/src/cpu/amd/agesa/romstage.c +++ b/src/cpu/amd/agesa/romstage.c @@ -26,6 +26,7 @@ #include <romstage_handoff.h> #include <smp/node.h> #include <string.h> +#include <timestamp.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> @@ -60,6 +61,9 @@ void * asmlinkage romstage_main(unsigned long bist) if ((initial_apic_id == 0) && boot_cpu()) { + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + platform_once(cb); console_init(); @@ -77,11 +81,17 @@ void * asmlinkage romstage_main(unsigned long bist) agesa_execute_state(cb, AMD_INIT_EARLY); + timestamp_add_now(TS_BEFORE_INITRAM); + if (!cb->s3resume) agesa_execute_state(cb, AMD_INIT_POST); else agesa_execute_state(cb, AMD_INIT_RESUME); + /* FIXME: Detect if TSC frequency changed during raminit? */ + timestamp_rescale_table(1, 4); + timestamp_add_now(TS_AFTER_INITRAM); + } else { agesa_main(cb); |