diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-21 19:34:38 +0000 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-24 16:55:47 +0000 |
| commit | 71f69ddc79ab798682ed5c6051442c179f004577 (patch) | |
| tree | 8dc215b63a1f553822f76b6c3cfee37a65efed4c | |
| parent | 7f6ae79280eabce22f1df3c858617c6e890e3594 (diff) | |
Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE"
This reverts commit 2f8a7046bb120d96022ada1e74545f859f97521f.
Reason for revert: CB:54752 makes this unnecessary
Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5 files changed, 3 insertions, 21 deletions
diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index c3f8d229d6..475bf61148 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -17,6 +17,4 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) }; memcfg_init(&memupd->FspmConfig, mem_config, &spd_info, half_populated); - - variant_update_fspm_upds(memupd); } diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 1d1fe83ec2..fb105e806a 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -3,7 +3,6 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ -#include <fsp/api.h> #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> @@ -20,6 +19,4 @@ const struct mb_cfg *variant_memory_params(void); int variant_memory_sku(void); bool variant_is_half_populated(void); -void variant_update_fspm_upds(FSPM_UPD *memupd); - #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/brya/variants/brya0/Makefile.inc b/src/mainboard/google/brya/variants/brya0/Makefile.inc deleted file mode 100644 index b30586551f..0000000000 --- a/src/mainboard/google/brya/variants/brya0/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -romstage-y += variant.c -ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index ccc0384497..452e1d8789 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -122,6 +122,9 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie_rp6 on + probe DB_LTE LTE_PCIE + end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c deleted file mode 100644 index 554371ddac..0000000000 --- a/src/mainboard/google/brya/variants/brya0/variant.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <console/console.h> -#include <fw_config.h> - -void variant_update_fspm_upds(FSPM_UPD *memupd) -{ - if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_USB))) { - FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; - printk(BIOS_INFO, "Disabling PCIe RP 6 UPD for USB WWAN\n"); - m_cfg->PcieRpEnableMask &= ~BIT(5); - } -} |