diff options
| author | Sugnan Prabhu S <sugnan.prabhu.s@intel.com> | 2021-03-16 10:31:23 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-04-22 15:59:49 +0000 |
| commit | 70299d916891b718606cad151cf56b1d410cf96a (patch) | |
| tree | 6b68dc10eb9c6dd7c79a13eaa2a26fa992199572 | |
| parent | 50f8b4ebdd7db8077b87ab7686637599c9d93af3 (diff) | |
mb/google/brya: Enable display and DSP audio UPD
This patch includes changes to enable display and DSP audio UPD.
BUG=b:181219097,b:183482000
TEST=Audio sound card is detected and listed by the linux kernel.
Audio playback and capture is working on the Brya.
Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 4ef1da9bf9..6a15b9a240 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -71,6 +71,12 @@ chip soc/intel/alderlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |