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authorRobert Zieba <robertzieba@google.com>2022-10-04 12:06:38 -0600
committerFelix Held <felix-coreboot@felixheld.de>2023-03-09 19:39:09 +0000
commit6f8f482066cf2d7131d10659aa234f7faf3d688c (patch)
tree38f4504b9317ae2420c154eacfe72fefb10329e7
parent3b28aefa1d45d7a2531fb715c58dc40f75b53745 (diff)
mb/google/skyrim: Store XHCI PCI resourcess
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. Example elog contents: ``` 244 | 2022-10-11 15:49:24 | S0ix Enter 245 | 2022-10-11 15:49:29 | S0ix Exit 246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31 247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256 248 | 2022-10-11 15:50:08 | S0ix Enter 249 | 2022-10-11 15:50:16 | S0ix Exit 250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31 251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BUG=b:186792595 TEST=Ran on skyrim proto, verified that wake events show in elog Change-Id: I529f541a8932267a8825773ddc582beafb27da63 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68325 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/skyrim/mainboard.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c
index d36dfafbfd..475e5cfd47 100644
--- a/src/mainboard/google/skyrim/mainboard.c
+++ b/src/mainboard/google/skyrim/mainboard.c
@@ -3,8 +3,10 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/psp.h>
+#include <amdblocks/xhci.h>
#include <baseboard/variants.h>
#include <console/console.h>
+#include <cpu/x86/smm.h>
#include <device/device.h>
#include <drivers/i2c/tpm/chip.h>
#include <soc/acpi.h>
@@ -95,6 +97,11 @@ static void mainboard_enable(struct device *dev)
pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
}
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+ soc_xhci_store_resources(slots, size);
+}
+
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,