soc/amd/*/include/msr: drop _LO part from PSTATE definition names

The _LO part in the definition names is a leftover from before moving to
the pstate_msr union access to the bitfield elements where it still
mattered if a bit was in the lower of higher half of the MSR. With the
mask-and-shift access to the two parts of the MSR being gone, the _LO
part in the name isn't useful any more and possibly a bit misleading, so
drop that part.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib43c71e946388c944ecf40659d4c12ca02a27a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73927
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

10 files changed, 42 insertions, 42 deletions

diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index de3f46eab2..f65973d979 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -108,12 +108,12 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 
 	if (core_freq_div == 0) {
 		return 0;
-	} else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN)
-		   && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) {
+	} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
+		   && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
 		/* Allow 1/8 integer steps for this range */
 		valid_freq_divisor = true;
-	} else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX)
-		   && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
+	} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
+		   && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
 		/* Only allow 1/4 integer steps for this range */
 		valid_freq_divisor = true;
 	} else {
@@ -123,11 +123,11 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 	if (valid_freq_divisor) {
 		/* 25 * core_freq_mul / (core_freq_div / 8) */
 		core_freq =
-			((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
+			((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
 	} else {
 		printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
 		       core_freq_div);
-		core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul);
+		core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
 	}
 	return core_freq;
 }
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h
index 8163cf8000..2ce03ade8a 100644
--- a/src/soc/amd/cezanne/include/soc/msr.h
+++ b/src/soc/amd/cezanne/include/soc/msr.h
@@ -17,10 +17,10 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define PSTATE_DEF_LO_FREQ_DIV_MIN	0x8
-#define PSTATE_DEF_LO_EIGHTH_STEP_MAX	0x1A
-#define PSTATE_DEF_LO_FREQ_DIV_MAX	0x3E
-#define PSTATE_DEF_LO_CORE_FREQ_BASE	25
+#define PSTATE_DEF_FREQ_DIV_MIN		0x8
+#define PSTATE_DEF_EIGHTH_STEP_MAX	0x1A
+#define PSTATE_DEF_FREQ_DIV_MAX		0x3E
+#define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
 #define  SERIAL_VID_DECODE_MICROVOLTS	6250
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index ce0c7e6001..1accc962d4 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -106,7 +106,7 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 	core_freq_mul = pstate_reg.cpu_fid_0_11;
 
 	/* CPU frequency is 5 * core_freq_mul */
-	return PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul;
+	return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul;
 }
 
 uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h
index 2c5b933b96..3f9254971c 100644
--- a/src/soc/amd/glinda/include/soc/msr.h
+++ b/src/soc/amd/glinda/include/soc/msr.h
@@ -20,7 +20,7 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define PSTATE_DEF_LO_CORE_FREQ_BASE	5
+#define PSTATE_DEF_CORE_FREQ_BASE	5
 
 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
 #define  SERIAL_VID_DECODE_MICROVOLTS	5000
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c
index 3b557806cc..3248adb6b5 100644
--- a/src/soc/amd/mendocino/acpi.c
+++ b/src/soc/amd/mendocino/acpi.c
@@ -110,12 +110,12 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 
 	if (core_freq_div == 0) {
 		return 0;
-	} else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN)
-		   && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) {
+	} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
+		   && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
 		/* Allow 1/8 integer steps for this range */
 		valid_freq_divisor = true;
-	} else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX)
-		   && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
+	} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
+		   && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
 		/* Only allow 1/4 integer steps for this range */
 		valid_freq_divisor = true;
 	} else {
@@ -125,11 +125,11 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 	if (valid_freq_divisor) {
 		/* 25 * core_freq_mul / (core_freq_div / 8) */
 		core_freq =
-			((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
+			((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
 	} else {
 		printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
 		       core_freq_div);
-		core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul);
+		core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
 	}
 	return core_freq;
 }
diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h
index 496c6df29c..39babf46d0 100644
--- a/src/soc/amd/mendocino/include/soc/msr.h
+++ b/src/soc/amd/mendocino/include/soc/msr.h
@@ -17,10 +17,10 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define PSTATE_DEF_LO_FREQ_DIV_MIN	0x8
-#define PSTATE_DEF_LO_EIGHTH_STEP_MAX	0x1A
-#define PSTATE_DEF_LO_FREQ_DIV_MAX	0x3E
-#define PSTATE_DEF_LO_CORE_FREQ_BASE	25
+#define PSTATE_DEF_FREQ_DIV_MIN		0x8
+#define PSTATE_DEF_EIGHTH_STEP_MAX	0x1A
+#define PSTATE_DEF_FREQ_DIV_MAX		0x3E
+#define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
 #define  SERIAL_VID_DECODE_MICROVOLTS	5000
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index 1be00f9828..4fae1c9d74 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -111,12 +111,12 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 
 	if (core_freq_div == 0) {
 		return 0;
-	} else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN)
-		   && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) {
+	} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
+		   && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
 		/* Allow 1/8 integer steps for this range */
 		valid_freq_divisor = true;
-	} else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX)
-		   && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
+	} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
+		   && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
 		/* Only allow 1/4 integer steps for this range */
 		valid_freq_divisor = true;
 	} else {
@@ -126,11 +126,11 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 	if (valid_freq_divisor) {
 		/* 25 * core_freq_mul / (core_freq_div / 8) */
 		core_freq =
-			((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
+			((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
 	} else {
 		printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
 		       core_freq_div);
-		core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul);
+		core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
 	}
 	return core_freq;
 }
diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h
index 8ac48bfd36..ef7a2e2260 100644
--- a/src/soc/amd/phoenix/include/soc/msr.h
+++ b/src/soc/amd/phoenix/include/soc/msr.h
@@ -20,10 +20,10 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define PSTATE_DEF_LO_FREQ_DIV_MIN	0x8
-#define PSTATE_DEF_LO_EIGHTH_STEP_MAX	0x1A
-#define PSTATE_DEF_LO_FREQ_DIV_MAX	0x3E
-#define PSTATE_DEF_LO_CORE_FREQ_BASE	25
+#define PSTATE_DEF_FREQ_DIV_MIN		0x8
+#define PSTATE_DEF_EIGHTH_STEP_MAX	0x1A
+#define PSTATE_DEF_FREQ_DIV_MAX		0x3E
+#define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
 #define  SERIAL_VID_DECODE_MICROVOLTS	5000
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 1c6456e1f0..3a2157bea1 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -112,12 +112,12 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 
 	if (core_freq_div == 0) {
 		return 0;
-	} else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN)
-		   && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) {
+	} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
+		   && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
 		/* Allow 1/8 integer steps for this range */
 		valid_freq_divisor = true;
-	} else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX)
-		   && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
+	} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
+		   && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
 		/* Only allow 1/4 integer steps for this range */
 		valid_freq_divisor = true;
 	} else {
@@ -127,11 +127,11 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
 	if (valid_freq_divisor) {
 		/* 25 * core_freq_mul / (core_freq_div / 8) */
 		core_freq =
-			((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
+			((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
 	} else {
 		printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
 		       core_freq_div);
-		core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul);
+		core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
 	}
 	return core_freq;
 }
diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h
index 05cda1ca89..83f5f0596f 100644
--- a/src/soc/amd/picasso/include/soc/msr.h
+++ b/src/soc/amd/picasso/include/soc/msr.h
@@ -21,10 +21,10 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define PSTATE_DEF_LO_FREQ_DIV_MIN	0x8
-#define PSTATE_DEF_LO_EIGHTH_STEP_MAX	0x1A
-#define PSTATE_DEF_LO_FREQ_DIV_MAX	0x3E
-#define PSTATE_DEF_LO_CORE_FREQ_BASE	25
+#define PSTATE_DEF_FREQ_DIV_MIN		0x8
+#define PSTATE_DEF_EIGHTH_STEP_MAX	0x1A
+#define PSTATE_DEF_FREQ_DIV_MAX		0x3E
+#define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
 #define  SERIAL_VID_DECODE_MICROVOLTS	6250