soc/intel/xeon_sp/spr: Add common device tree

Add common device tree used for EGS platform. Also add register
setting shared for all EGS platform.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I812f621ee9d1643fd4fa35df92443d64f7aaabc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

2 files changed, 89 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 0c60f8c2f7..b1d92cfdd2 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -8,6 +8,10 @@ config SOC_SPECIFIC_OPTIONS
 	select SAVE_MRC_AFTER_FSPS
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 
+config CHIPSET_DEVICETREE
+	string
+	default "soc/intel/xeon_sp/spr/chipset.cb"
+
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
 	depends on MAINBOARD_USES_FSP2_0
diff --git a/src/soc/intel/xeon_sp/spr/chipset.cb b/src/soc/intel/xeon_sp/spr/chipset.cb
new file mode 100644
index 0000000000..efc8637a56
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/chipset.cb
@@ -0,0 +1,85 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/spr
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# configure device interrupt routing
+	register "ir00_routing" = "0x3210" # IR00, Dev31
+	register "ir01_routing" = "0x3210" # IR01, Dev30
+	register "ir02_routing" = "0x3210" # IR02, Dev29
+	register "ir03_routing" = "0x3210" # IR03, Dev28
+	register "ir04_routing" = "0x3210" # IR04, Dev27
+
+	# configure interrupt polarity control
+	register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+	register "ipc1" = "0x00000000" # IPC1
+	register "ipc2" = "0x00000000" # IPC2
+	register "ipc3" = "0x00000000" # IPC3
+
+	# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
+	register "pstate_req_ratio" = "0xa"
+
+	# configure VT-d
+	register "vtd_support" = "1"
+
+	register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
+	register "cstate_states" = "CSTATES_C1C6"
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on end # Intel device 09a2: Memory Map/Intel VT-d
+		device pci 00.1 on end # Intel device 09a4: Mesh to IAL
+		device pci 00.4 on end # Intel device 0b23: IEH
+		device pci 00.2 on end # Intel device 09a3: RAS
+		device pci 01.0 on end # Intel device 3c01: Port A PCIe Gen5
+		device pci 02.0 on end # Intel device 3c01: Port D PCIe Gen4
+		device pci 03.0 on end # Intel device 3c01: Port B PCIe Gen5
+		device pci 04.0 on end # Intel device 3c01: Port C PCIe Gen4
+		device pci 05.0 on end # Intel device 3c01: Port C PCIe Gen5
+		device pci 06.0 on end # Intel device 3c01: Port B PCIe Gen4
+		device pci 07.0 on end # Intel device 3c01: Port D PCIe Gen5
+		device pci 08.0 on end # Intel device 2020: DMI
+		device pci 09.0 on end # Intel device 1bb9: PCH PCIe Root Port #1
+		device pci 0a.0 on end # Intel device 1bba: PCH PCIe Root Port #2
+		device pci 0b.0 on end # Intel device 1bbb: PCH PCIe Root Port #3
+		device pci 0c.0 on end # Intel device 1bbc: PCH PCIe Root Port #4
+		device pci 0d.0 on end # Intel device 1bbd: PCH PCIe Root Port #5
+		device pci 0e.0 on end # Intel device 1bbe: PCH PCIe Root Port #6
+		device pci 0f.0 on end # Intel device 1bbf: PCH PCIe Root Port #7
+		device pci 10.0 on end # Intel device 1bb0: PCH PCIe Root Port #8
+		device pci 11.0 on end # Intel device 1bb1: PCH PCIe Root Port #9
+		device pci 12.0 on end # Intel device 1bb2: PCH PCIe Root Port #10
+		device pci 13.0 on end # Intel device 1bb3: PCH PCIe Root Port #11
+		device pci 14.0 on end # Intel device 1bcd: PCH USB 3.0 XHCI Controller
+		device pci 14.2 on end # Intel device 1bce: PCH PMC shared RAM
+		device pci 15.0 on end # Intel device 1bff
+		device pci 16.0 on end # Intel device 1be0: PCH ME HECI #1
+		device pci 16.1 on end # Intel device 1be1: PCH ME HECI #2
+		device pci 16.3 on end # Serial controller: Intel Corporation Device 1be3
+		device pci 16.4 on end # Intel device 1be4: PCH ME HECI #3
+		device pci 16.5 on end # Intel device 1be5: PCH ME HECI #4
+		device pci 16.6 on end # Intel device 1be6
+		device pci 17.0 on end # Intel device 1ba2: PCH SATA controller (AHCI)
+		device pci 1a.0 on end # Intel device 1bb4: PCH PCIe Root Port #12
+		device pci 1b.0 on end # Intel device 1bb5: PCH PCIe Root Port #13
+		device pci 1e.0 on end # Intel device Communication controller: Intel Corporation Device 1bad
+		device pci 1f.0 on end # Intel device 1b81: PCH eSPI controller
+		device pci 1f.1 on end # Intel device 1bc6: PCH P2SB
+		device pci 1f.2 on end # Intel device 1bc7: PCH PMC
+		device pci 1f.3 on end # Intel device 1bc8: PCH audio
+		device pci 1f.4 on end # Intel device 1bc9: PCH SMBus
+		device pci 1f.5 on end # Intel device 1bca: PCH SPI controller
+		device pci 1f.6 on end # Intel device 1bcb: PCH GbE controller
+		device pci 1f.7 on end # Intel device 1bcc: PCH TH
+
+	end
+end