diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2020-10-02 12:59:43 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:38:27 +0000 |
| commit | 6745056a06fa2e69cc23bc797a7a69bb6c0e2b58 (patch) | |
| tree | a5d4cf67bf0dd156ca792dfb5c23a52943b22fd7 | |
| parent | 1f8af4f49b9556eb5540948f664549c07af58ef4 (diff) | |
util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.
BUG=b:161772961
TEST=none
Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/tigerlake/spd/ddr4-spd-9.hex | 32 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt | 1 | ||||
| -rw-r--r-- | util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt | 12 |
3 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex new file mode 100644 index 0000000000..1ce7c21d4c --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt index 202f1734d4..21565c66b6 100644 --- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt @@ -13,3 +13,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex H5ANAG6NDMR-XNC,ddr4-spd-2.hex +H5ANAG6NCJR-XNC,ddr4-spd-9.hex diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt index 776bce7d2b..72b0ccd9aa 100644 --- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt +++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt @@ -191,6 +191,18 @@ "packageBusWidth": 16, "ranksPerPackage": 1 } + }, + { + // Datasheet Revision: Rev. 1.4, May. 2020 + "name": "H5ANAG6NCJR-XNC", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 16, + "diesPerPackage": 1, + "packageBusWidth": 16, + "ranksPerPackage": 1 + } } ] } |