diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2018-03-22 06:29:57 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-25 11:43:53 +0000 |
| commit | 6681cf0966f02917dbb4dc8d667c59688193828d (patch) | |
| tree | 9b2acc009f8b7d484f4b64d3d5db0c67eaf18145 | |
| parent | f2b4993b1d060dcc05b1794b0319dc7903fd6fa0 (diff) | |
soc/intel/apollolake: Sync FSP PCIE NPK device as per devicetree
This patch makes our devicetree in sync with the FSP configuration.
Without this we see in boot logs "PCI: 00:00.2 not found,
disabling it". The reason being in FSP NPK device is disabled by
default. We can enable it by enabling the UPD parameter TraceHubEn.
If we enable it in FSP then the logs complain the NPK pcie device
is not seen.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not report
"PCI: 00:00.2 not found, disabling it".
Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pci_devs.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 13 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 6aa2520b55..25b74babc0 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -48,6 +48,10 @@ /* PCH Devices */ +#define PCH_DEV_SLOT_NPK 0x00 +#define PCH_DEVFN_NPK _PCH_DEVFN(NPK, 2) +#define PCH_DEV_NPK _PCH_DEV(NPK,2) + #define PCH_DEV_SLOT_P2SB 0x0d #define PCH_DEVFN_P2SB _PCH_DEVFN(P2SB, 0) #define PCH_DEVFN_PMC _PCH_DEVFN(P2SB, 1) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 3d695ea52f..6a2007e937 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -319,6 +319,17 @@ static void soc_memory_init_params(FSPM_UPD *mupd) #endif } +static void parse_devicetree_setting(FSPM_UPD *m_upd) +{ +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK); + if (!dev) + return; + + m_upd->FspmConfig.TraceHubEn = dev->enabled; +#endif +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { struct region_device rdev; @@ -332,6 +343,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mainboard_memory_init_params(mupd); + parse_devicetree_setting(mupd); + /* Do NOT let FSP do any GPIO pad configuration */ mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; |