diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-12-08 15:17:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-10 08:02:19 +0000 |
| commit | 650de582207c63c3592bdb3867557e5c968974ba (patch) | |
| tree | efedc0646af24e233de8c61b09c929d3594124d9 | |
| parent | 9a598588884fd879de34ae1ef1b5bae57cc60c1e (diff) | |
soc/intel/alderlake: Move TCSS FW latency macros to tcss.h
This patch moves TCSS firmware latency related macros from
`tcss_pcierp.asl` to SoC specific `tcss.h`.
TEST=Able to build and boot Google/Kano.
Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss.asl | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_pcierp.asl | 20 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/tcss.h | 20 |
3 files changed, 21 insertions, 20 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 87aeb73b8d..0890e4048c 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <soc/iomap.h> +#include <soc/tcss.h> /* * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index dee265c3a3..7336e162a8 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -1,25 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency - * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream - * port of the USB4/TBT topology. - */ -/* Number of microseconds to wait after a conventional reset */ -#define FW_RESET_TIME 50000 - -/* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 - -/* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 - -/* Number of microseconds to wait from D3 hot to D0 transition */ -#define FW_D3HOT_TO_D0_TIME 50000 - -/* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 - OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) Field (PXCS, AnyAcc, NoLock, Preserve) { diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h index 014e3076e6..05baf5d534 100644 --- a/src/soc/intel/alderlake/include/soc/tcss.h +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -13,4 +13,24 @@ #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) +/* + * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency + * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream + * port of the USB4/TBT topology. + */ +/* Number of microseconds to wait after a conventional reset */ +#define FW_RESET_TIME 50000 + +/* Number of microseconds to wait after data link layer active report */ +#define FW_DL_UP_TIME 1 + +/* Number of microseconds to wait after a function level reset */ +#define FW_FLR_RESET_TIME 1 + +/* Number of microseconds to wait from D3 hot to D0 transition */ +#define FW_D3HOT_TO_D0_TIME 50000 + +/* Number of microseconds to wait after setting the VF enable bit */ +#define FW_VF_ENABLE_TIME 1 + #endif /* _SOC_TCSS_H_ */ |