diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 13:02:22 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-24 16:10:53 +0000 |
| commit | 61615e95e268b84cd10b9921ac0f18e0896246f0 (patch) | |
| tree | c6ef7330bec580ec1da5b60e60dbe0ed8561d122 | |
| parent | d0bf24750623561fd2ea3d349853e061224931b2 (diff) | |
soc/intel/broadwell: Do early ME init a bit earlier
Do early ME init before adding the "start of raminit" timestamp.
Change-Id: If8b27a9d4eb3b801e3e05dc2f2b95bf748985707
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55800
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/broadwell/romstage.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 0ba62589eb..08895f80d0 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -54,6 +54,13 @@ void mainboard_romstage_entry(void) /* Initialize GPIOs */ setup_pch_lp_gpios(mainboard_lp_gpio_map); + /* Print ME state before MRC */ + intel_me_status(); + + /* Save ME HSIO version */ + intel_me_hsio_version(&power_state->hsio_version, + &power_state->hsio_checksum); + mainboard_fill_pei_data(&pei_data); mainboard_fill_spd_data(&pei_data); @@ -63,13 +70,6 @@ void mainboard_romstage_entry(void) pei_data.boot_mode = power_state->prev_sleep_state; - /* Print ME state before MRC */ - intel_me_status(); - - /* Save ME HSIO version */ - intel_me_hsio_version(&power_state->hsio_version, - &power_state->hsio_checksum); - /* Initialize RAM */ sdram_initialize(&pei_data); |