diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2016-07-25 14:44:51 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-27 19:36:01 +0200 |
| commit | 60cc75df83f2da64132b6da6dd431417da6b2f4e (patch) | |
| tree | f80c68566c35d5adb8bc1fdc34731bb583f17a14 | |
| parent | 46114517d73df66a47e93fb38732ca9cbd3d0c5f (diff) | |
soc/intel/apollolake: Disable monitor mwait
The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around
BUG=chrome-os-partner:55110
Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c71e59a26c..544cd133c8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -394,6 +394,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ + silconfig->MonitorMwaitEnable = 0; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; } |