diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-10-17 10:31:30 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-11-03 13:53:18 +0100 |
| commit | 60687b52076ec6d4da3587859adcb0d49a05aca0 (patch) | |
| tree | 3426873e778930b4aa548d9abfdaba61d010ef36 | |
| parent | d36ed272b2d2d082889a7f21414904badc2c2936 (diff) | |
rockchip/rk3399: sdram.c: Fix msch ddrconfig register error
Fix msch ddrconfig register write error. Also make sure that the row
number configured in msch is equal to the row number configured in the
DDR controller.
This would not affect systems with 4GB of memory, but is needed
for 2GB configurations.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: Ic95b3371faec5b31c32b011c50e55e83d949e74d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dfa43d3d44839d9685b6393157f51b646e9996de
Original-Change-Id: I0c95378bf937a245b7cdc0583c5d2ed1347f2a3e
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/399563
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17208
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/rockchip/rk3399/sdram.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9ff1294bcd..4ea31dde1f 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -153,6 +153,14 @@ static void set_memory_map(u32 channel, u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; u32 cs_map; u32 reduc; + u32 row; + + if ((sdram_ch->ddrconfig < 2) || (sdram_ch->ddrconfig == 4)) + row = 16; + else if (sdram_ch->ddrconfig == 3) + row = 14; + else + row = 15; cs_map = (sdram_ch->rank > 1) ? 3 : 1; reduc = (sdram_ch->bw == 2) ? 0 : 1; @@ -160,7 +168,7 @@ static void set_memory_map(u32 channel, clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), ((3 - sdram_ch->bk) << 16) | - ((16 - sdram_ch->cs0_row) << 24)); + ((16 - row) << 24)); clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), cs_map | (reduc << 16)); @@ -171,7 +179,7 @@ static void set_memory_map(u32 channel, /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), ((3 - sdram_ch->bk) << 16) | - ((16 - sdram_ch->cs0_row) << 24)); + ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3)) @@ -869,7 +877,7 @@ static void set_ddrconfig(const struct rk3399_sdram_params *sdram_params, cs1_cap = cs1_cap * 3 / 4; } - write32(&ddr_msch_regs->ddrconf, ddrconfig | (ddrconfig << 6)); + write32(&ddr_msch_regs->ddrconf, ddrconfig | (ddrconfig << 8)); write32(&ddr_msch_regs->ddrsize, ((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8)); } |