diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-08 12:29:01 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-10 13:15:33 +0000 |
| commit | 5d2b1e6e467d291b2aef9b192299692c5ad9c535 (patch) | |
| tree | f01297718d4c35e7c3dc5dfa56b1c1c59b0c9d4c | |
| parent | f9fe704a83df752cb81803382cf99eadfb37fd29 (diff) | |
soc/intel/apollolake: Let coreboot set the VendorID and Subsystem ID
Set all FSP S UPDs that set IDs to 0, which allows them to be set
by coreboot.
Tested on StarLite Mk IV and LPC now has the correct device ID of
0x31e8, where previously it had 0x7270.
The UPDs differ APL and GLK, but the ones configured in this patch
have been there since their initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I034c9dc9d81c4d775dfff0994c9a6be823689b1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 40316a203d..bab39bb4b6 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -615,6 +615,11 @@ static void glk_fsp_silicon_init_params_cb( * Options to adjust PMIC Vdd2 voltage. */ silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; + + /* FSP should let coreboot set subsystem IDs, which are read/write-once */ + silconfig->SiSVID = 0; + silconfig->SiSSID = 0; + silconfig->HgSubSystemId = 0; #endif } @@ -724,6 +729,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); silconfig->Timer8254ClkSetting = use_8254; + /* FSP should let coreboot set subsystem IDs, which are read/write-once */ + silconfig->SubSystemVendorId = 0; + silconfig->SubSystemId = 0; + mainboard_silicon_init_params(silconfig); } |