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authorPoornima Tom <poornima.tom@intel.corp-partner.google.com>2024-06-14 03:23:43 +0530
committerSubrata Banik <subratabanik@google.com>2024-06-28 03:52:41 +0000
commit5a0e7f5be09465b38e3b2a5ab179629c2a48f4cf (patch)
tree21bc144ddef1d3090018d5e191fd21b43deea37d
parentf930b9faaec9ebf4440e79d4eb289072d3cd13a0 (diff)
mb/google/nissa/var/nivviks: Enable wifi7 on pcie root port
Enable pcie based, discreete wifi7 on root port4. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi7 module detection based on cbi settings Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/brya/variants/nivviks/overridetree.cb24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index 45280167f7..22dd9ca2ac 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -503,6 +503,30 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
+ device ref pcie_rp4 on
+ probe WIFI_CATEGORY WIFI_7
+ # Enable WLAN Card PCIE 4 using clk 2
+ register "pch_pcie_rp[PCH_RP(4)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_DW1_03"
+ register "add_acpi_dma_property" = "true"
+ device pci 00.0 on
+ probe WIFI_CATEGORY WIFI_7
+ end
+ end
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+ register "srcclk_pin" = "2"
+ device generic 0 on
+ probe WIFI_CATEGORY WIFI_7
+ end
+ end
+ end #PCIE4 WLAN card
device ref pcie_rp7 on
# Enable SD Card PCIe 7 using clk 3
register "pch_pcie_rp[PCH_RP(7)]" = "{