diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-11-17 15:50:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-26 11:20:14 +0000 |
| commit | 580150de460c9b87d78acac6c42f6c0b4e545bc2 (patch) | |
| tree | 83175566f530d878cb298341a6135a6dea6cc08d | |
| parent | 9234d9231b177c80281805301d4c67c8ca4d02bb (diff) | |
mb/google/corsola: configure GPIOs
Configure Chromebook specific GPIOs, including EC_AP_INT,
EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/mainboard/google/corsola/bootblock.c | 3 | ||||
| -rw-r--r-- | src/mainboard/google/corsola/chromeos.c | 21 | ||||
| -rw-r--r-- | src/mainboard/google/corsola/gpio.h | 19 |
3 files changed, 42 insertions, 1 deletions
diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index e9ae5cefe7..bb76b983a9 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -4,7 +4,10 @@ #include <device/mmio.h> #include <soc/spi.h> +#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_snfc_init(SPI_NOR_GPIO_SET0); + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 3f0937f693..6a727c9897 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -2,10 +2,29 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <gpio.h> -void fill_lb_gpios(struct lb_gpios *gpios) +#include "gpio.h" + +void setup_chromeos_gpios(void) { + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_GSC_AP_INT); + gpio_output(GPIO_EN_SPK, 0); + gpio_output(GPIO_RESET, 0); +} +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_GSC_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/corsola/gpio.h b/src/mainboard/google/corsola/gpio.h new file mode 100644 index 0000000000..78dd252050 --- /dev/null +++ b/src/mainboard/google/corsola/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CORSOLA_GPIO_H__ +#define __MAINBOARD_GOOGLE_CORSOLA_GPIO_H__ + +#include <soc/gpio.h> + +#define GPIO_EC_AP_INT GPIO(EINT13) +#define GPIO_WP GPIO(EINT16) +#define GPIO_BEEP_ON GPIO(PERIPHERAL_EN4) +#define GPIO_XHCI_DONE GPIO(PERIPHERAL_EN1) +#define GPIO_EC_IN_RW GPIO(EINT14) +#define GPIO_GSC_AP_INT GPIO(EINT15) +#define GPIO_EN_SPK GPIO(PERIPHERAL_EN3) +#define GPIO_RESET GPIO(PERIPHERAL_EN0) + +void setup_chromeos_gpios(void); + +#endif |