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authorFelix Held <felix-coreboot@felixheld.de>2018-07-28 00:41:57 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-07-29 17:28:05 +0000
commit55823c3d36d783a856b60e7b216cae05b2f470c4 (patch)
tree32d8d8dacdb3cdafab803db5ea1aecab4e013b6e
parentb9267f0cec6677cfb215fab955756e5f9aefe3b5 (diff)
sandybridge/raminit: use MCHBAR32 macro everywhere
Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 31c7d5bc5b..f646a7706e 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -335,10 +335,10 @@ static void init_dram_ddr3(int min_tck, int s3resume)
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
- reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000
+ reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000
if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
&& reg_5d10 && !s3resume) {
- write32(DEFAULT_MCHBAR + 0x5d10, 0);
+ MCHBAR32(0x5d10) = 0;
/* Need reset. */
outb(0x6, 0xcf9);
@@ -438,7 +438,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
die("raminit failed");
/* FIXME: should be hardware revision-dependent. */
- write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);
+ MCHBAR32(0x5024) = 0x00a030ce;
set_scrambling_seed(&ctrl);